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sys/dev/ice/ice_adminq_cmd.h
Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines | |||||
#define ICE_AQC_CAPS_IWARP 0x0051 | #define ICE_AQC_CAPS_IWARP 0x0051 | ||||
#define ICE_AQC_CAPS_LED 0x0061 | #define ICE_AQC_CAPS_LED 0x0061 | ||||
#define ICE_AQC_CAPS_SDP 0x0062 | #define ICE_AQC_CAPS_SDP 0x0062 | ||||
#define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 | #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 | ||||
#define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 | #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 | ||||
#define ICE_AQC_CAPS_SKU 0x0074 | #define ICE_AQC_CAPS_SKU 0x0074 | ||||
#define ICE_AQC_CAPS_PORT_MAP 0x0075 | #define ICE_AQC_CAPS_PORT_MAP 0x0075 | ||||
#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 | #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 | ||||
#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 | |||||
#define ICE_AQC_CAPS_NVM_MGMT 0x0080 | #define ICE_AQC_CAPS_NVM_MGMT 0x0080 | ||||
u8 major_ver; | u8 major_ver; | ||||
u8 minor_ver; | u8 minor_ver; | ||||
/* Number of resources described by this capability */ | /* Number of resources described by this capability */ | ||||
__le32 number; | __le32 number; | ||||
/* Only meaningful for some types of resources */ | /* Only meaningful for some types of resources */ | ||||
__le32 logical_id; | __le32 logical_id; | ||||
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines | struct { | ||||
__le16 num_desc; | __le16 num_desc; | ||||
__le16 reserved; | __le16 reserved; | ||||
} resp; | } resp; | ||||
} ops; | } ops; | ||||
__le32 addr_high; | __le32 addr_high; | ||||
__le32 addr_low; | __le32 addr_low; | ||||
}; | }; | ||||
/* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ | |||||
struct ice_aqc_set_vlan_mode { | |||||
u8 reserved; | |||||
u8 l2tag_prio_tagging; | |||||
#define ICE_AQ_VLAN_PRIO_TAG_S 0 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) | |||||
#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 | |||||
#define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 | |||||
u8 l2tag_reserved[64]; | |||||
u8 rdma_packet; | |||||
#define ICE_AQ_VLAN_RDMA_TAG_S 0 | |||||
#define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) | |||||
#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 | |||||
#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A | |||||
u8 rdma_reserved[2]; | |||||
u8 mng_vlan_prot_id; | |||||
#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 | |||||
#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 | |||||
u8 prot_id_reserved[30]; | |||||
}; | |||||
/* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ | |||||
struct ice_aqc_get_vlan_mode { | |||||
u8 vlan_mode; | |||||
#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) | |||||
u8 l2tag_prio_tagging; | |||||
u8 reserved[98]; | |||||
}; | |||||
/* Add VSI (indirect 0x0210) | /* Add VSI (indirect 0x0210) | ||||
* Update VSI (indirect 0x0211) | * Update VSI (indirect 0x0211) | ||||
* Get VSI (indirect 0x0212) | * Get VSI (indirect 0x0212) | ||||
* Free VSI (indirect 0x0213) | * Free VSI (indirect 0x0213) | ||||
*/ | */ | ||||
struct ice_aqc_add_get_update_free_vsi { | struct ice_aqc_add_get_update_free_vsi { | ||||
__le16 vsi_num; | __le16 vsi_num; | ||||
#define ICE_AQ_VSI_NUM_S 0 | #define ICE_AQ_VSI_NUM_S 0 | ||||
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) | ||||
/* switch section */ | /* switch section */ | ||||
u8 sw_id; | u8 sw_id; | ||||
u8 sw_flags; | u8 sw_flags; | ||||
#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) | #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) | ||||
#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) | #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) | ||||
#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) | #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) | ||||
u8 sw_flags2; | u8 sw_flags2; | ||||
#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 | #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 | ||||
#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ | #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) | ||||
(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) | |||||
#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) | #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) | ||||
#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) | #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) | ||||
u8 veb_stat_id; | u8 veb_stat_id; | ||||
#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 | #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 | ||||
#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) | #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) | ||||
#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) | #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) | ||||
/* security section */ | /* security section */ | ||||
u8 sec_flags; | u8 sec_flags; | ||||
#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) | #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) | ||||
#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) | #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) | ||||
#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 | #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 | ||||
#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) | #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) | ||||
#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) | #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) | ||||
u8 sec_reserved; | u8 sec_reserved; | ||||
/* VLAN section */ | /* VLAN section */ | ||||
__le16 pvid; /* VLANS include priority bits */ | __le16 port_based_inner_vlan; /* VLANS include priority bits */ | ||||
u8 pvlan_reserved[2]; | u8 inner_vlan_reserved[2]; | ||||
u8 vlan_flags; | u8 inner_vlan_flags; | ||||
#define ICE_AQ_VSI_VLAN_MODE_S 0 | #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 | ||||
#define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S) | #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) | ||||
#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1 | #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 | ||||
#define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2 | #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 | ||||
#define ICE_AQ_VSI_VLAN_MODE_ALL 0x3 | #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 | ||||
#define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) | #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) | ||||
#define ICE_AQ_VSI_VLAN_EMOD_S 3 | #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 | ||||
#define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) | #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) | ||||
#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S) | #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) | ||||
#define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S) | #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) | ||||
#define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S) | #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) | ||||
#define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S) | #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) | ||||
u8 pvlan_reserved2[3]; | #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) | ||||
u8 inner_vlan_reserved2[3]; | |||||
/* ingress egress up sections */ | /* ingress egress up sections */ | ||||
__le32 ingress_table; /* bitmap, 3 bits per up */ | __le32 ingress_table; /* bitmap, 3 bits per up */ | ||||
#define ICE_AQ_VSI_UP_TABLE_UP0_S 0 | #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) | #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP1_S 3 | #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) | #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP2_S 6 | #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) | #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP3_S 9 | #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) | #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP4_S 12 | #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) | #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP5_S 15 | #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) | #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP6_S 18 | #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) | #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) | ||||
#define ICE_AQ_VSI_UP_TABLE_UP7_S 21 | #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 | ||||
#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) | #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) | ||||
__le32 egress_table; /* same defines as for ingress table */ | __le32 egress_table; /* same defines as for ingress table */ | ||||
/* outer tags section */ | /* outer tags section */ | ||||
__le16 outer_tag; | __le16 port_based_outer_vlan; | ||||
u8 outer_tag_flags; | u8 outer_vlan_flags; | ||||
#define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 | #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 | ||||
#define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) | #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) | ||||
#define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 | #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 | ||||
#define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 | #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 | ||||
#define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 | #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 | ||||
#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 | |||||
#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 | #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 | ||||
#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) | #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) | ||||
#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 | #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 | ||||
#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 | #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 | ||||
#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 | #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 | ||||
#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 | #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 | ||||
#define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) | #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) | ||||
#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) | #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 | ||||
u8 outer_tag_reserved; | #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) | ||||
#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 | |||||
#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 | |||||
#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 | |||||
#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) | |||||
u8 outer_vlan_reserved; | |||||
/* queue mapping section */ | /* queue mapping section */ | ||||
__le16 mapping_flags; | __le16 mapping_flags; | ||||
#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 | #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 | ||||
#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) | #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) | ||||
__le16 q_mapping[16]; | __le16 q_mapping[16]; | ||||
#define ICE_AQ_VSI_Q_S 0 | #define ICE_AQ_VSI_Q_S 0 | ||||
#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) | #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) | ||||
__le16 tc_mapping[8]; | __le16 tc_mapping[8]; | ||||
#define ICE_AQ_VSI_TC_Q_OFFSET_S 0 | #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 | ||||
#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) | #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) | ||||
#define ICE_AQ_VSI_TC_Q_NUM_S 11 | #define ICE_AQ_VSI_TC_Q_NUM_S 11 | ||||
#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) | #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) | ||||
/* queueing option section */ | /* queueing option section */ | ||||
u8 q_opt_rss; | u8 q_opt_rss; | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 | #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) | #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 | #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | ||||
#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | ||||
u8 q_opt_tc; | u8 q_opt_tc; | ||||
#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 | #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 | ||||
#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) | #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) | ||||
#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) | #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) | ||||
u8 q_opt_flags; | u8 q_opt_flags; | ||||
#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) | #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) | ||||
u8 q_opt_reserved[3]; | u8 q_opt_reserved[3]; | ||||
/* outer up section */ | /* outer up section */ | ||||
__le32 outer_up_table; /* same structure and defines as ingress tbl */ | __le32 outer_up_table; /* same structure and defines as ingress tbl */ | ||||
/* section 10 */ | /* section 10 */ | ||||
__le16 sect_10_reserved; | __le16 sect_10_reserved; | ||||
/* flow director section */ | /* flow director section */ | ||||
__le16 fd_options; | __le16 fd_options; | ||||
#define ICE_AQ_VSI_FD_ENABLE BIT(0) | #define ICE_AQ_VSI_FD_ENABLE BIT(0) | ||||
#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) | #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) | ||||
#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) | #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) | ||||
__le16 max_fd_fltr_dedicated; | __le16 max_fd_fltr_dedicated; | ||||
__le16 max_fd_fltr_shared; | __le16 max_fd_fltr_shared; | ||||
__le16 fd_def_q; | __le16 fd_def_q; | ||||
#define ICE_AQ_VSI_FD_DEF_Q_S 0 | #define ICE_AQ_VSI_FD_DEF_Q_S 0 | ||||
#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) | #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) | ||||
#define ICE_AQ_VSI_FD_DEF_GRP_S 12 | #define ICE_AQ_VSI_FD_DEF_GRP_S 12 | ||||
#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) | #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) | ||||
__le16 fd_report_opt; | __le16 fd_report_opt; | ||||
#define ICE_AQ_VSI_FD_REPORT_Q_S 0 | #define ICE_AQ_VSI_FD_REPORT_Q_S 0 | ||||
#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) | #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) | ||||
#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 | #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 | ||||
#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) | #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) | ||||
#define ICE_AQ_VSI_FD_DEF_DROP BIT(15) | #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) | ||||
/* PASID section */ | /* PASID section */ | ||||
__le32 pasid_id; | __le32 pasid_id; | ||||
#define ICE_AQ_VSI_PASID_ID_S 0 | #define ICE_AQ_VSI_PASID_ID_S 0 | ||||
#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) | #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) | ||||
#define ICE_AQ_VSI_PASID_ID_VALID BIT(31) | #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) | ||||
u8 reserved[24]; | u8 reserved[24]; | ||||
}; | }; | ||||
/* Add/update mirror rule - direct (0x0260) */ | /* Add/update mirror rule - direct (0x0260) */ | ||||
#define ICE_AQC_RULE_ID_VALID_S 7 | #define ICE_AQC_RULE_ID_VALID_S 7 | ||||
#define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) | #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) | ||||
#define ICE_AQC_RULE_ID_S 0 | #define ICE_AQC_RULE_ID_S 0 | ||||
#define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) | #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) | ||||
▲ Show 20 Lines • Show All 361 Lines • ▼ Show 20 Lines | struct ice_aqc_sched_elem_cmd { | ||||
__le32 addr_high; | __le32 addr_high; | ||||
__le32 addr_low; | __le32 addr_low; | ||||
}; | }; | ||||
struct ice_aqc_txsched_move_grp_info_hdr { | struct ice_aqc_txsched_move_grp_info_hdr { | ||||
__le32 src_parent_teid; | __le32 src_parent_teid; | ||||
__le32 dest_parent_teid; | __le32 dest_parent_teid; | ||||
__le16 num_elems; | __le16 num_elems; | ||||
__le16 reserved; | u8 flags; | ||||
u8 reserved; | |||||
}; | }; | ||||
struct ice_aqc_move_elem { | struct ice_aqc_move_elem { | ||||
struct ice_aqc_txsched_move_grp_info_hdr hdr; | struct ice_aqc_txsched_move_grp_info_hdr hdr; | ||||
__le32 teid[STRUCT_HACK_VAR_LEN]; | __le32 teid[STRUCT_HACK_VAR_LEN]; | ||||
}; | }; | ||||
struct ice_aqc_elem_info_bw { | struct ice_aqc_elem_info_bw { | ||||
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines | |||||
/* Get PHY capabilities (indirect 0x0600) */ | /* Get PHY capabilities (indirect 0x0600) */ | ||||
struct ice_aqc_get_phy_caps { | struct ice_aqc_get_phy_caps { | ||||
u8 lport_num; | u8 lport_num; | ||||
u8 reserved; | u8 reserved; | ||||
__le16 param0; | __le16 param0; | ||||
/* 18.0 - Report qualified modules */ | /* 18.0 - Report qualified modules */ | ||||
#define ICE_AQC_GET_PHY_RQM BIT(0) | #define ICE_AQC_GET_PHY_RQM BIT(0) | ||||
/* 18.1 - 18.2 : Report mode | /* 18.1 - 18.3 : Report mode | ||||
* 00b - Report NVM capabilities | * 000b - Report NVM capabilities | ||||
* 01b - Report topology capabilities | * 001b - Report topology capabilities | ||||
* 10b - Report SW configured | * 010b - Report SW configured | ||||
* 100b - Report default capabilities | |||||
*/ | */ | ||||
#define ICE_AQC_REPORT_MODE_S 1 | #define ICE_AQC_REPORT_MODE_S 1 | ||||
#define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) | #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) | ||||
#define ICE_AQC_REPORT_NVM_CAP 0 | #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 | ||||
#define ICE_AQC_REPORT_TOPO_CAP BIT(1) | #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) | ||||
#define ICE_AQC_REPORT_SW_CFG BIT(2) | #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) | ||||
#define ICE_AQC_REPORT_DFLT_CFG BIT(3) | |||||
__le32 reserved1; | __le32 reserved1; | ||||
__le32 addr_high; | __le32 addr_high; | ||||
__le32 addr_low; | __le32 addr_low; | ||||
}; | }; | ||||
/* This is #define of PHY type (Extended): | /* This is #define of PHY type (Extended): | ||||
* The first set of defines is for phy_type_low. | * The first set of defines is for phy_type_low. | ||||
*/ | */ | ||||
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#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) | #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) | ||||
#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) | #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) | ||||
#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) | #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) | ||||
#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) | #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) | ||||
#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) | #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) | ||||
#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) | #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) | ||||
#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) | #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) | ||||
u8 link_cfg_err; | u8 link_cfg_err; | ||||
#define ICE_AQ_LINK_CFG_ERR BIT(0) | #define ICE_AQ_LINK_CFG_ERR BIT(0) | ||||
#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) | #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) | ||||
#define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) | #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) | ||||
#define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) | #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) | ||||
#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) | #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) | ||||
#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) | |||||
#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) | |||||
u8 link_info; | u8 link_info; | ||||
#define ICE_AQ_LINK_UP BIT(0) /* Link Status */ | #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ | ||||
#define ICE_AQ_LINK_FAULT BIT(1) | #define ICE_AQ_LINK_FAULT BIT(1) | ||||
#define ICE_AQ_LINK_FAULT_TX BIT(2) | #define ICE_AQ_LINK_FAULT_TX BIT(2) | ||||
#define ICE_AQ_LINK_FAULT_RX BIT(3) | #define ICE_AQ_LINK_FAULT_RX BIT(3) | ||||
#define ICE_AQ_LINK_FAULT_REMOTE BIT(4) | #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) | ||||
#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ | #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ | ||||
#define ICE_AQ_MEDIA_AVAILABLE BIT(6) | #define ICE_AQ_MEDIA_AVAILABLE BIT(6) | ||||
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Lines | |||||
#define ICE_AQC_PORT_OPT_COUNT_S 0 | #define ICE_AQC_PORT_OPT_COUNT_S 0 | ||||
#define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) | #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) | ||||
u8 innermost_phy_index; | u8 innermost_phy_index; | ||||
u8 port_options; | u8 port_options; | ||||
#define ICE_AQC_PORT_OPT_ACTIVE_S 0 | #define ICE_AQC_PORT_OPT_ACTIVE_S 0 | ||||
#define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) | #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) | ||||
#define ICE_AQC_PORT_OPT_FORCED BIT(6) | #define ICE_AQC_PORT_OPT_FORCED BIT(6) | ||||
#define ICE_AQC_PORT_OPT_VALID BIT(7) | #define ICE_AQC_PORT_OPT_VALID BIT(7) | ||||
u8 rsvd[3]; | u8 pending_port_option_status; | ||||
#define ICE_AQC_PENDING_PORT_OPT_IDX_S 0 | |||||
#define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S) | |||||
#define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) | |||||
u8 rsvd[2]; | |||||
__le32 addr_high; | __le32 addr_high; | ||||
__le32 addr_low; | __le32 addr_low; | ||||
}; | }; | ||||
struct ice_aqc_get_port_options_elem { | struct ice_aqc_get_port_options_elem { | ||||
u8 pmd; | u8 pmd; | ||||
#define ICE_AQC_PORT_INV_PORT_OPT 4 | #define ICE_AQC_PORT_INV_PORT_OPT 4 | ||||
#define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 | #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 | ||||
#define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) | #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) | ||||
#define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 | #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 | ||||
#define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) | #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) | ||||
u8 max_lane_speed; | u8 max_lane_speed; | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_S 0 | #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) | #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 | #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 | #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 | #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 | #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 | #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 | #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 | #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 | ||||
#define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 | #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 | ||||
u8 global_scid[2]; | u8 global_scid[2]; | ||||
u8 phy_scid[2]; | u8 phy_scid[2]; | ||||
u8 pf2port_cid[2]; | |||||
}; | }; | ||||
/* Set Port Option (direct, 0x06EB) */ | /* Set Port Option (direct, 0x06EB) */ | ||||
struct ice_aqc_set_port_option { | struct ice_aqc_set_port_option { | ||||
u8 lport_num; | u8 lport_num; | ||||
u8 lport_num_valid; | u8 lport_num_valid; | ||||
#define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) | #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) | ||||
u8 selected_port_option; | u8 selected_port_option; | ||||
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines | |||||
#define ICE_AQC_SW_GPIO_NUMBER_S 0 | #define ICE_AQC_SW_GPIO_NUMBER_S 0 | ||||
#define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) | #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) | ||||
u8 gpio_params; | u8 gpio_params; | ||||
#define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) | #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) | ||||
#define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) | #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) | ||||
u8 rsvd[12]; | u8 rsvd[12]; | ||||
}; | }; | ||||
/* Program topology device NVM (direct, 0x06F2) */ | |||||
struct ice_aqc_program_topology_device_nvm { | |||||
u8 lport_num; | |||||
u8 lport_num_valid; | |||||
u8 node_type_ctx; | |||||
u8 index; | |||||
u8 rsvd[12]; | |||||
}; | |||||
/* Read topology device NVM (indirect, 0x06F3) */ | |||||
struct ice_aqc_read_topology_device_nvm { | |||||
u8 lport_num; | |||||
u8 lport_num_valid; | |||||
u8 node_type_ctx; | |||||
u8 index; | |||||
__le32 start_address; | |||||
u8 data_read[8]; | |||||
}; | |||||
/* NVM Read command (indirect 0x0701) | /* NVM Read command (indirect 0x0701) | ||||
* NVM Erase commands (direct 0x0702) | * NVM Erase commands (direct 0x0702) | ||||
* NVM Write commands (indirect 0x0703) | * NVM Write commands (indirect 0x0703) | ||||
* NVM Write Activate commands (direct 0x0707) | * NVM Write Activate commands (direct 0x0707) | ||||
* NVM Shadow RAM Dump commands (direct 0x0707) | * NVM Shadow RAM Dump commands (direct 0x0707) | ||||
*/ | */ | ||||
struct ice_aqc_nvm { | struct ice_aqc_nvm { | ||||
#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF | #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF | ||||
Show All 13 Lines | |||||
#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) | #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) | ||||
#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) | #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) | ||||
#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ | #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ | ||||
#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) | #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) | ||||
#define ICE_AQC_NVM_FLASH_ONLY BIT(7) | #define ICE_AQC_NVM_FLASH_ONLY BIT(7) | ||||
#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ | #define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ | ||||
#define ICE_AQC_NVM_PERST_FLAG 1 | #define ICE_AQC_NVM_PERST_FLAG 1 | ||||
#define ICE_AQC_NVM_EMPR_FLAG 2 | #define ICE_AQC_NVM_EMPR_FLAG 2 | ||||
#define ICE_AQC_NVM_EMPR_ENA BIT(0) | |||||
__le16 module_typeid; | __le16 module_typeid; | ||||
__le16 length; | __le16 length; | ||||
#define ICE_AQC_NVM_ERASE_LEN 0xFFFF | #define ICE_AQC_NVM_ERASE_LEN 0xFFFF | ||||
__le32 addr_high; | __le32 addr_high; | ||||
__le32 addr_low; | __le32 addr_low; | ||||
}; | }; | ||||
/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ | /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ | ||||
▲ Show 20 Lines • Show All 601 Lines • ▼ Show 20 Lines | #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) | ||||
__le32 internal_data2; | __le32 internal_data2; | ||||
}; | }; | ||||
/* Clear Health Status (direct 0xFF23) */ | /* Clear Health Status (direct 0xFF23) */ | ||||
struct ice_aqc_clear_health_status { | struct ice_aqc_clear_health_status { | ||||
__le32 reserved[4]; | __le32 reserved[4]; | ||||
}; | }; | ||||
/* Set FW Logging configuration (indirect 0xFF30) | |||||
* Register for FW Logging (indirect 0xFF31) | |||||
* Query FW Logging (indirect 0xFF32) | |||||
* FW Log Event (indirect 0xFF33) | |||||
* Get FW Log (indirect 0xFF34) | |||||
* Clear FW Log (indirect 0xFF35) | |||||
*/ | |||||
struct ice_aqc_fw_log { | |||||
u8 cmd_flags; | |||||
#define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) | |||||
#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) | |||||
#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) | |||||
#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) | |||||
#define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) | |||||
#define ICE_AQC_FW_LOG_PERSISTENT BIT(0) | |||||
u8 rsp_flag; | |||||
#define ICE_AQC_FW_LOG_MORE_DATA BIT(1) | |||||
__le16 fw_rt_msb; | |||||
union { | |||||
struct { | |||||
__le32 fw_rt_lsb; | |||||
} sync; | |||||
struct { | |||||
__le16 log_resolution; | |||||
#define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) | |||||
#define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) | |||||
__le16 mdl_cnt; | |||||
} cfg; | |||||
} ops; | |||||
__le32 addr_high; | |||||
__le32 addr_low; | |||||
}; | |||||
/* Response Buffer for: | |||||
* Set Firmware Logging Configuration (0xFF30) | |||||
* Query FW Logging (0xFF32) | |||||
*/ | |||||
struct ice_aqc_fw_log_cfg_resp { | |||||
__le16 module_identifier; | |||||
u8 log_level; | |||||
u8 rsvd0; | |||||
}; | |||||
/** | /** | ||||
* struct ice_aq_desc - Admin Queue (AQ) descriptor | * struct ice_aq_desc - Admin Queue (AQ) descriptor | ||||
* @flags: ICE_AQ_FLAG_* flags | * @flags: ICE_AQ_FLAG_* flags | ||||
* @opcode: AQ command opcode | * @opcode: AQ command opcode | ||||
* @datalen: length in bytes of indirect/external data buffer | * @datalen: length in bytes of indirect/external data buffer | ||||
* @retval: return value from firmware | * @retval: return value from firmware | ||||
* @cookie_high: opaque data high-half | * @cookie_high: opaque data high-half | ||||
* @cookie_low: opaque data low-half | * @cookie_low: opaque data low-half | ||||
Show All 35 Lines | union { | ||||
struct ice_aqc_dnl_run_command dnl_run; | struct ice_aqc_dnl_run_command dnl_run; | ||||
struct ice_aqc_dnl_call_command dnl_call; | struct ice_aqc_dnl_call_command dnl_call; | ||||
struct ice_aqc_dnl_read_write_command dnl_read_write; | struct ice_aqc_dnl_read_write_command dnl_read_write; | ||||
struct ice_aqc_dnl_read_write_response dnl_read_write_resp; | struct ice_aqc_dnl_read_write_response dnl_read_write_resp; | ||||
struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; | struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; | ||||
struct ice_aqc_dnl_read_log_command dnl_read_log; | struct ice_aqc_dnl_read_log_command dnl_read_log; | ||||
struct ice_aqc_dnl_read_log_response dnl_read_log_resp; | struct ice_aqc_dnl_read_log_response dnl_read_log_resp; | ||||
struct ice_aqc_i2c read_write_i2c; | struct ice_aqc_i2c read_write_i2c; | ||||
struct ice_aqc_read_i2c_resp read_i2c_resp; | |||||
struct ice_aqc_mdio read_write_mdio; | struct ice_aqc_mdio read_write_mdio; | ||||
struct ice_aqc_gpio_by_func read_write_gpio_by_func; | struct ice_aqc_gpio_by_func read_write_gpio_by_func; | ||||
struct ice_aqc_gpio read_write_gpio; | struct ice_aqc_gpio read_write_gpio; | ||||
struct ice_aqc_set_led set_led; | struct ice_aqc_set_led set_led; | ||||
struct ice_aqc_mdio read_mdio; | |||||
struct ice_aqc_mdio write_mdio; | |||||
struct ice_aqc_sff_eeprom read_write_sff_param; | struct ice_aqc_sff_eeprom read_write_sff_param; | ||||
struct ice_aqc_set_port_id_led set_port_id_led; | struct ice_aqc_set_port_id_led set_port_id_led; | ||||
struct ice_aqc_get_port_options get_port_options; | struct ice_aqc_get_port_options get_port_options; | ||||
struct ice_aqc_set_port_option set_port_option; | struct ice_aqc_set_port_option set_port_option; | ||||
struct ice_aqc_get_sw_cfg get_sw_conf; | struct ice_aqc_get_sw_cfg get_sw_conf; | ||||
struct ice_aqc_set_port_params set_port_params; | struct ice_aqc_set_port_params set_port_params; | ||||
struct ice_aqc_sw_rules sw_rules; | struct ice_aqc_sw_rules sw_rules; | ||||
struct ice_aqc_storm_cfg storm_conf; | struct ice_aqc_storm_cfg storm_conf; | ||||
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines | enum ice_adminq_opc { | ||||
ice_aqc_opc_get_sw_cfg = 0x0200, | ice_aqc_opc_get_sw_cfg = 0x0200, | ||||
ice_aqc_opc_set_port_params = 0x0203, | ice_aqc_opc_set_port_params = 0x0203, | ||||
/* Alloc/Free/Get Resources */ | /* Alloc/Free/Get Resources */ | ||||
ice_aqc_opc_get_res_alloc = 0x0204, | ice_aqc_opc_get_res_alloc = 0x0204, | ||||
ice_aqc_opc_alloc_res = 0x0208, | ice_aqc_opc_alloc_res = 0x0208, | ||||
ice_aqc_opc_free_res = 0x0209, | ice_aqc_opc_free_res = 0x0209, | ||||
ice_aqc_opc_get_allocd_res_desc = 0x020A, | ice_aqc_opc_get_allocd_res_desc = 0x020A, | ||||
ice_aqc_opc_set_vlan_mode_parameters = 0x020C, | |||||
ice_aqc_opc_get_vlan_mode_parameters = 0x020D, | |||||
/* VSI commands */ | /* VSI commands */ | ||||
ice_aqc_opc_add_vsi = 0x0210, | ice_aqc_opc_add_vsi = 0x0210, | ||||
ice_aqc_opc_update_vsi = 0x0211, | ice_aqc_opc_update_vsi = 0x0211, | ||||
ice_aqc_opc_get_vsi_params = 0x0212, | ice_aqc_opc_get_vsi_params = 0x0212, | ||||
ice_aqc_opc_free_vsi = 0x0213, | ice_aqc_opc_free_vsi = 0x0213, | ||||
/* Mirroring rules - add/update, delete */ | /* Mirroring rules - add/update, delete */ | ||||
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines | enum ice_adminq_opc { | ||||
ice_aqc_opc_set_port_id_led = 0x06E9, | ice_aqc_opc_set_port_id_led = 0x06E9, | ||||
ice_aqc_opc_get_port_options = 0x06EA, | ice_aqc_opc_get_port_options = 0x06EA, | ||||
ice_aqc_opc_set_port_option = 0x06EB, | ice_aqc_opc_set_port_option = 0x06EB, | ||||
ice_aqc_opc_set_gpio = 0x06EC, | ice_aqc_opc_set_gpio = 0x06EC, | ||||
ice_aqc_opc_get_gpio = 0x06ED, | ice_aqc_opc_get_gpio = 0x06ED, | ||||
ice_aqc_opc_sff_eeprom = 0x06EE, | ice_aqc_opc_sff_eeprom = 0x06EE, | ||||
ice_aqc_opc_sw_set_gpio = 0x06EF, | ice_aqc_opc_sw_set_gpio = 0x06EF, | ||||
ice_aqc_opc_sw_get_gpio = 0x06F0, | ice_aqc_opc_sw_get_gpio = 0x06F0, | ||||
ice_aqc_opc_program_topology_device_nvm = 0x06F2, | |||||
ice_aqc_opc_read_topology_device_nvm = 0x06F3, | |||||
/* NVM commands */ | /* NVM commands */ | ||||
ice_aqc_opc_nvm_read = 0x0701, | ice_aqc_opc_nvm_read = 0x0701, | ||||
ice_aqc_opc_nvm_erase = 0x0702, | ice_aqc_opc_nvm_erase = 0x0702, | ||||
ice_aqc_opc_nvm_write = 0x0703, | ice_aqc_opc_nvm_write = 0x0703, | ||||
ice_aqc_opc_nvm_cfg_read = 0x0704, | ice_aqc_opc_nvm_cfg_read = 0x0704, | ||||
ice_aqc_opc_nvm_cfg_write = 0x0705, | ice_aqc_opc_nvm_cfg_write = 0x0705, | ||||
ice_aqc_opc_nvm_checksum = 0x0706, | ice_aqc_opc_nvm_checksum = 0x0706, | ||||
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines | enum ice_adminq_opc { | ||||
/* Standalone Commands/Events */ | /* Standalone Commands/Events */ | ||||
ice_aqc_opc_event_lan_overflow = 0x1001, | ice_aqc_opc_event_lan_overflow = 0x1001, | ||||
/* SystemDiagnostic commands */ | /* SystemDiagnostic commands */ | ||||
ice_aqc_opc_set_health_status_config = 0xFF20, | ice_aqc_opc_set_health_status_config = 0xFF20, | ||||
ice_aqc_opc_get_supported_health_status_codes = 0xFF21, | ice_aqc_opc_get_supported_health_status_codes = 0xFF21, | ||||
ice_aqc_opc_get_health_status = 0xFF22, | ice_aqc_opc_get_health_status = 0xFF22, | ||||
ice_aqc_opc_clear_health_status = 0xFF23 | ice_aqc_opc_clear_health_status = 0xFF23, | ||||
/* FW Logging Commands */ | |||||
ice_aqc_opc_fw_logs_config = 0xFF30, | |||||
ice_aqc_opc_fw_logs_register = 0xFF31, | |||||
ice_aqc_opc_fw_logs_query = 0xFF32, | |||||
ice_aqc_opc_fw_logs_event = 0xFF33, | |||||
ice_aqc_opc_fw_logs_get = 0xFF34, | |||||
ice_aqc_opc_fw_logs_clear = 0xFF35 | |||||
}; | }; | ||||
#endif /* _ICE_ADMINQ_CMD_H_ */ | #endif /* _ICE_ADMINQ_CMD_H_ */ |