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usr.sbin/bhyve/pci_virtio_console.c
Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Lines | static struct virtio_consts vtcon_vi_consts = { | ||||
"vtcon", /* our name */ | "vtcon", /* our name */ | ||||
VTCON_MAXQ, /* we support VTCON_MAXQ virtqueues */ | VTCON_MAXQ, /* we support VTCON_MAXQ virtqueues */ | ||||
sizeof(struct pci_vtcon_config), /* config reg size */ | sizeof(struct pci_vtcon_config), /* config reg size */ | ||||
pci_vtcon_reset, /* reset */ | pci_vtcon_reset, /* reset */ | ||||
NULL, /* device-wide qnotify */ | NULL, /* device-wide qnotify */ | ||||
pci_vtcon_cfgread, /* read virtio config */ | pci_vtcon_cfgread, /* read virtio config */ | ||||
pci_vtcon_cfgwrite, /* write virtio config */ | pci_vtcon_cfgwrite, /* write virtio config */ | ||||
pci_vtcon_neg_features, /* apply negotiated features */ | pci_vtcon_neg_features, /* apply negotiated features */ | ||||
VTCON_S_HOSTCAPS, /* our capabilities */ | VTCON_S_HOSTCAPS, /* our capabilities (legacy) */ | ||||
VTCON_S_HOSTCAPS, /* our capabilities (modern) */ | |||||
true, /* Enable legacy */ | |||||
true, /* Enable modern */ | |||||
2, /* PCI BAR# for modern */ | |||||
}; | }; | ||||
static void | static void | ||||
pci_vtcon_reset(void *vsc) | pci_vtcon_reset(void *vsc) | ||||
{ | { | ||||
struct pci_vtcon_softc *sc; | struct pci_vtcon_softc *sc; | ||||
▲ Show 20 Lines • Show All 515 Lines • ▼ Show 20 Lines | pci_vtcon_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) | ||||
for (i = 0; i < VTCON_MAXQ; i++) { | for (i = 0; i < VTCON_MAXQ; i++) { | ||||
sc->vsc_queues[i].vq_qsize = VTCON_RINGSZ; | sc->vsc_queues[i].vq_qsize = VTCON_RINGSZ; | ||||
sc->vsc_queues[i].vq_notify = i % 2 == 0 | sc->vsc_queues[i].vq_notify = i % 2 == 0 | ||||
? pci_vtcon_notify_rx | ? pci_vtcon_notify_rx | ||||
: pci_vtcon_notify_tx; | : pci_vtcon_notify_tx; | ||||
} | } | ||||
/* initialize config space */ | /* initialize config space */ | ||||
pci_set_cfgdata16(pi, PCIR_DEVICE, VIRTIO_DEV_CONSOLE); | pci_set_cfgdata16(pi, PCIR_DEVICE, sc->vsc_vs.vs_vc->vc_en_legacy ? | ||||
VIRTIO_DEV_CONSOLE : vi_get_modern_pci_devid(VIRTIO_ID_CONSOLE)); | |||||
pci_set_cfgdata16(pi, PCIR_VENDOR, VIRTIO_VENDOR); | pci_set_cfgdata16(pi, PCIR_VENDOR, VIRTIO_VENDOR); | ||||
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SIMPLECOMM); | pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SIMPLECOMM); | ||||
pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_ID_CONSOLE); | pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_ID_CONSOLE); | ||||
pci_set_cfgdata16(pi, PCIR_SUBVEND_0, VIRTIO_VENDOR); | pci_set_cfgdata16(pi, PCIR_SUBVEND_0, VIRTIO_VENDOR); | ||||
if (vi_intr_init(&sc->vsc_vs, 1, fbsdrun_virtio_msix())) | if (vi_intr_init(&sc->vsc_vs, 1, fbsdrun_virtio_msix())) | ||||
return (1); | return (1); | ||||
vi_set_io_bar(&sc->vsc_vs, 0); | vi_setup_pci_bar(&sc->vsc_vs); | ||||
/* create control port */ | /* create control port */ | ||||
sc->vsc_control_port.vsp_sc = sc; | sc->vsc_control_port.vsp_sc = sc; | ||||
sc->vsc_control_port.vsp_txq = 2; | sc->vsc_control_port.vsp_txq = 2; | ||||
sc->vsc_control_port.vsp_rxq = 3; | sc->vsc_control_port.vsp_rxq = 3; | ||||
sc->vsc_control_port.vsp_cb = pci_vtcon_control_tx; | sc->vsc_control_port.vsp_cb = pci_vtcon_control_tx; | ||||
sc->vsc_control_port.vsp_enabled = true; | sc->vsc_control_port.vsp_enabled = true; | ||||
Show All 19 Lines | pci_vtcon_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) | ||||
} | } | ||||
return (0); | return (0); | ||||
} | } | ||||
struct pci_devemu pci_de_vcon = { | struct pci_devemu pci_de_vcon = { | ||||
.pe_emu = "virtio-console", | .pe_emu = "virtio-console", | ||||
.pe_init = pci_vtcon_init, | .pe_init = pci_vtcon_init, | ||||
.pe_cfgwrite = vi_pci_cfgwrite, | |||||
.pe_cfgread = vi_pci_cfgread, | |||||
.pe_barwrite = vi_pci_write, | .pe_barwrite = vi_pci_write, | ||||
.pe_barread = vi_pci_read | .pe_barread = vi_pci_read | ||||
}; | }; | ||||
PCI_EMUL_SET(pci_de_vcon); | PCI_EMUL_SET(pci_de_vcon); |