Differential D29584 Diff 89548 sys/dev/smartpqi/smartpqi_sis.c

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sys/dev/smartpqi/smartpqi_sis.c

/*-		/*-
* Copyright (c) 2018 Microsemi Corporation.		* Copyright 2016-2021 Microchip Technology, Inc. and/or its subsidiaries.
* All rights reserved.
*		*
* Redistribution and use in source and binary forms, with or without		* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions		* modification, are permitted provided that the following conditions
* are met:		* are met:
* 1. Redistributions of source code must retain the above copyright		* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.		* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright		* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the		* notice, this list of conditions and the following disclaimer in the
Show All 11 Lines
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF		* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.		* SUCH DAMAGE.
*/		*/

/* $FreeBSD$ */		/* $FreeBSD$ */

#include "smartpqi_includes.h"		#include "smartpqi_includes.h"

/* */		/* Function for disabling msix interrupots */
void sis_disable_msix(pqisrc_softstate_t *softs)		void
		sis_disable_msix(pqisrc_softstate_t *softs)
{		{
uint32_t db_reg;		uint32_t db_reg;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,		db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR);		LEGACY_SIS_IDBR);
db_reg &= ~SIS_ENABLE_MSIX;		db_reg &= ~SIS_ENABLE_MSIX;
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,		PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR, db_reg);		LEGACY_SIS_IDBR, db_reg);

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
}		}

void sis_enable_intx(pqisrc_softstate_t *softs)		void
		sis_enable_intx(pqisrc_softstate_t *softs)
{		{
uint32_t db_reg;		uint32_t db_reg;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,		db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR);		LEGACY_SIS_IDBR);
db_reg \|= SIS_ENABLE_INTX;		db_reg \|= SIS_ENABLE_INTX;
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,		PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR, db_reg);		LEGACY_SIS_IDBR, db_reg);
if (pqisrc_sis_wait_for_db_bit_to_clear(softs,SIS_ENABLE_INTX)		if (pqisrc_sis_wait_for_db_bit_to_clear(softs,SIS_ENABLE_INTX)
!= PQI_STATUS_SUCCESS) {		!= PQI_STATUS_SUCCESS) {
DBG_ERR("Failed to wait for enable intx db bit to clear\n");		DBG_ERR("Failed to wait for enable intx db bit to clear\n");
}		}
DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
}		}

void sis_disable_intx(pqisrc_softstate_t *softs)		void
		sis_disable_intx(pqisrc_softstate_t *softs)
{		{
uint32_t db_reg;		uint32_t db_reg;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,		db_reg = PCI_MEM_GET32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR);		LEGACY_SIS_IDBR);
db_reg &= ~SIS_ENABLE_INTX;		db_reg &= ~SIS_ENABLE_INTX;
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,		PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR, db_reg);		LEGACY_SIS_IDBR, db_reg);

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
}		}

void sis_disable_interrupt(pqisrc_softstate_t *softs)		void
		sis_disable_interrupt(pqisrc_softstate_t *softs)
{		{
DBG_FUNC("IN");		DBG_FUNC("IN");

switch(softs->intr_type) {		switch(softs->intr_type) {
case INTR_TYPE_FIXED:		case INTR_TYPE_FIXED:
pqisrc_configure_legacy_intx(softs,false);		pqisrc_configure_legacy_intx(softs,false);
sis_disable_intx(softs);		sis_disable_intx(softs);
break;		break;
case INTR_TYPE_MSI:		case INTR_TYPE_MSI:
case INTR_TYPE_MSIX:		case INTR_TYPE_MSIX:
sis_disable_msix(softs);		sis_disable_msix(softs);
break;		break;
default:		default:
DBG_ERR("Inerrupt mode none!\n");		DBG_ERR("Inerrupt mode none!\n");
break;		break;
}		}

DBG_FUNC("OUT");		DBG_FUNC("OUT");
}		}


/* Trigger a NMI as part of taking controller offline procedure */		/* Trigger a NMI as part of taking controller offline procedure */
void pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs)		void
		pqisrc_trigger_nmi_sis(pqisrc_softstate_t *softs)
{		{

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,		PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR, LE_32(TRIGGER_NMI_SIS));		LEGACY_SIS_IDBR, LE_32(TRIGGER_NMI_SIS));
DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
}		}

/* Switch the adapter back to SIS mode during uninitialization */		/* Switch the adapter back to SIS mode during uninitialization */
int pqisrc_reenable_sis(pqisrc_softstate_t *softs)		int
		pqisrc_reenable_sis(pqisrc_softstate_t *softs)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t timeout = SIS_ENABLE_TIMEOUT;		uint32_t timeout = SIS_ENABLE_TIMEOUT;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,		PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR, LE_32(REENABLE_SIS));		LEGACY_SIS_IDBR, LE_32(REENABLE_SIS));

COND_WAIT(((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &		COND_WAIT(((PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R) &
REENABLE_SIS) == 0), timeout)		REENABLE_SIS) == 0), timeout)
if (!timeout) {		if (!timeout) {
DBG_WARN(" [ %s ] failed to re enable sis\n",__func__);		DBG_WARN(" [ %s ] failed to re enable sis\n",__func__);
ret = PQI_STATUS_TIMEOUT;		ret = PQI_STATUS_TIMEOUT;
}		}

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
return ret;		return ret;
}		}

/* Validate the FW status PQI_CTRL_KERNEL_UP_AND_RUNNING */		/* Validate the FW status PQI_CTRL_KERNEL_UP_AND_RUNNING */
int pqisrc_check_fw_status(pqisrc_softstate_t *softs)		int
		pqisrc_check_fw_status(pqisrc_softstate_t *softs)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t timeout = SIS_STATUS_OK_TIMEOUT;		uint32_t timeout = SIS_STATUS_OK_TIMEOUT;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

OS_SLEEP(1000000);		OS_SLEEP(1000000);
COND_WAIT((GET_FW_STATUS(softs) &		COND_WAIT((GET_FW_STATUS(softs) &
PQI_CTRL_KERNEL_UP_AND_RUNNING), timeout);		PQI_CTRL_KERNEL_UP_AND_RUNNING), timeout);
if (!timeout) {		if (!timeout) {
DBG_ERR("FW check status timedout\n");		DBG_ERR("FW check status timedout\n");
ret = PQI_STATUS_TIMEOUT;		ret = PQI_STATUS_TIMEOUT;
}		}

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
return ret;		return ret;
}		}

/* Function used to submit a SIS command to the adapter */		/* Function used to submit a SIS command to the adapter */
static int pqisrc_send_sis_cmd(pqisrc_softstate_t *softs,		static int
uint32_t *mb)		pqisrc_send_sis_cmd(pqisrc_softstate_t softs, uint32_t mb)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
int i = 0;		int i = 0;
uint32_t timeout = SIS_CMD_COMPLETE_TIMEOUT;		uint32_t timeout = SIS_CMD_COMPLETE_TIMEOUT;

int val;		int val;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");


/* Copy Command to mailbox */		/* Copy Command to mailbox */
for (i = 0; i < 6; i++)		for (i = 0; i < 6; i++)
PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],		PCI_MEM_PUT32(softs, &softs->ioa_reg->mb[i],
LEGACY_SIS_SRCV_MAILBOX+i*4, LE_32(mb[i]));		LEGACY_SIS_SRCV_MAILBOX+i*4, LE_32(mb[i]));

		/* TODO : Switch to INTX Mode ?*/
PCI_MEM_PUT32(softs, &softs->ioa_reg->ioa_to_host_db_clr,		PCI_MEM_PUT32(softs, &softs->ioa_reg->ioa_to_host_db_clr,
LEGACY_SIS_ODBR_R, LE_32(0x1000));		LEGACY_SIS_ODBR_R, LE_32(0x1000));

/* Submit the command */		/* Submit the command */
PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,		PCI_MEM_PUT32(softs, &softs->ioa_reg->host_to_ioa_db,
LEGACY_SIS_IDBR, LE_32(SIS_CMD_SUBMIT));		LEGACY_SIS_IDBR, LE_32(SIS_CMD_SUBMIT));

#ifdef SIS_POLL_WAIT		#ifdef SIS_POLL_WAIT
/* Wait for 20 milli sec to poll */		/* Wait for 20 milli sec to poll */
OS_BUSYWAIT(SIS_POLL_START_WAIT_TIME);		OS_BUSYWAIT(SIS_POLL_START_WAIT_TIME);
#endif		#endif

val = PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R);		val = PCI_MEM_GET32(softs, &softs->ioa_reg->ioa_to_host_db, LEGACY_SIS_ODBR_R);
Show All 25 Lines	#endif
return ret;		return ret;

err_out:		err_out:
DBG_FUNC("OUT failed\n");		DBG_FUNC("OUT failed\n");
return ret;		return ret;
}		}

/* First SIS command for the adapter to check PQI support */		/* First SIS command for the adapter to check PQI support */
int pqisrc_get_adapter_properties(pqisrc_softstate_t *softs,		int
		pqisrc_get_adapter_properties(pqisrc_softstate_t *softs,
uint32_t prop, uint32_t ext_prop)		uint32_t prop, uint32_t ext_prop)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t mb[6] = {0};		uint32_t mb[6] = {0};

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

mb[0] = SIS_CMD_GET_ADAPTER_PROPERTIES;		mb[0] = SIS_CMD_GET_ADAPTER_PROPERTIES;
ret = pqisrc_send_sis_cmd(softs, mb);		ret = pqisrc_send_sis_cmd(softs, mb);
if (!ret) {		if (!ret) {
DBG_INIT("GET_PROPERTIES prop = %x, ext_prop = %x\n",		DBG_INIT("GET_PROPERTIES prop = %x, ext_prop = %x\n",
mb[1], mb[4]);		mb[1], mb[4]);
*prop = mb[1];		*prop = mb[1];
*ext_prop = mb[4];		*ext_prop = mb[4];
}		}

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
return ret;		return ret;
}		}

/* Second SIS command to the adapter GET_COMM_PREFERRED_SETTINGS */		/* Second SIS command to the adapter GET_COMM_PREFERRED_SETTINGS */
int pqisrc_get_preferred_settings(pqisrc_softstate_t *softs)		int
		pqisrc_get_preferred_settings(pqisrc_softstate_t *softs)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t mb[6] = {0};		uint32_t mb[6] = {0};

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

mb[0] = SIS_CMD_GET_COMM_PREFERRED_SETTINGS;		mb[0] = SIS_CMD_GET_COMM_PREFERRED_SETTINGS;
ret = pqisrc_send_sis_cmd(softs, mb);		ret = pqisrc_send_sis_cmd(softs, mb);
if (!ret) {		if (!ret) {
/* 31:16 maximum command size in KB */		/* 31:16 maximum command size in KB */
softs->pref_settings.max_cmd_size = mb[1] >> 16;		softs->pref_settings.max_cmd_size = mb[1] >> 16;
/* 15:00: Maximum FIB size in bytes */		/* 15:00: Maximum FIB size in bytes */
softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF;		softs->pref_settings.max_fib_size = mb[1] & 0x0000FFFF;
DBG_INIT("cmd size = %x, fib size = %x\n",		DBG_INIT("cmd size = %x, fib size = %x\n",
softs->pref_settings.max_cmd_size,		softs->pref_settings.max_cmd_size,
softs->pref_settings.max_fib_size);		softs->pref_settings.max_fib_size);
}		}

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
return ret;		return ret;
}		}

/* Get supported PQI capabilities from the adapter */		/* Get supported PQI capabilities from the adapter */
int pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs)		int
		pqisrc_get_sis_pqi_cap(pqisrc_softstate_t *softs)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t mb[6] = {0};		uint32_t mb[6] = {0};

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

mb[0] = SIS_CMD_GET_PQI_CAPABILITIES;		mb[0] = SIS_CMD_GET_PQI_CAPABILITIES;
ret = pqisrc_send_sis_cmd(softs, mb);		ret = pqisrc_send_sis_cmd(softs, mb);
if (!ret) {		if (!ret) {
softs->pqi_cap.max_sg_elem = mb[1];		softs->pqi_cap.max_sg_elem = mb[1];
softs->pqi_cap.max_transfer_size = mb[2];		softs->pqi_cap.max_transfer_size = mb[2];
softs->pqi_cap.max_outstanding_io = mb[3];		softs->pqi_cap.max_outstanding_io = mb[3];
softs->pqi_cap.conf_tab_off = mb[4];		softs->pqi_cap.conf_tab_off = mb[4];
softs->pqi_cap.conf_tab_sz = mb[5];		softs->pqi_cap.conf_tab_sz = mb[5];

		os_update_dma_attributes(softs);

DBG_INIT("max_sg_elem = %x\n",		DBG_INIT("max_sg_elem = %x\n",
softs->pqi_cap.max_sg_elem);		softs->pqi_cap.max_sg_elem);
DBG_INIT("max_transfer_size = %x\n",		DBG_INIT("max_transfer_size = %x\n",
softs->pqi_cap.max_transfer_size);		softs->pqi_cap.max_transfer_size);
DBG_INIT("max_outstanding_io = %x\n",		DBG_INIT("max_outstanding_io = %x\n",
softs->pqi_cap.max_outstanding_io);		softs->pqi_cap.max_outstanding_io);
}		}

DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
return ret;		return ret;
}		}

/* Send INIT STRUCT BASE ADDR - one of the SIS command */		/* Send INIT STRUCT BASE ADDR - one of the SIS command */
int pqisrc_init_struct_base(pqisrc_softstate_t *softs)		int
		pqisrc_init_struct_base(pqisrc_softstate_t *softs)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t elem_size = 0;		uint32_t elem_size = 0;
uint32_t num_elem = 0;		uint32_t num_elem = 0;
struct dma_mem init_struct_mem = {0};		struct dma_mem init_struct_mem = {0};
struct init_base_struct *init_struct = NULL;		struct init_base_struct *init_struct = NULL;
uint32_t mb[6] = {0};		uint32_t mb[6] = {0};

▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines

/*		/*
* SIS initialization of the adapter in a sequence of		* SIS initialization of the adapter in a sequence of
* - GET_ADAPTER_PROPERTIES		* - GET_ADAPTER_PROPERTIES
* - GET_COMM_PREFERRED_SETTINGS		* - GET_COMM_PREFERRED_SETTINGS
* - GET_PQI_CAPABILITIES		* - GET_PQI_CAPABILITIES
* - INIT_STRUCT_BASE ADDR		* - INIT_STRUCT_BASE ADDR
*/		*/
int pqisrc_sis_init(pqisrc_softstate_t *softs)		int
		pqisrc_sis_init(pqisrc_softstate_t *softs)
{		{
int ret = PQI_STATUS_SUCCESS;		int ret = PQI_STATUS_SUCCESS;
uint32_t prop = 0;		uint32_t prop = 0;
uint32_t ext_prop = 0;		uint32_t ext_prop = 0;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

ret = pqisrc_force_sis(softs);		ret = pqisrc_force_sis(softs);
Show All 35 Lines	pqisrc_sis_init(pqisrc_softstate_t *softs)

/* Get PQI settings , 3000h*/		/* Get PQI settings , 3000h*/
ret = pqisrc_get_sis_pqi_cap(softs);		ret = pqisrc_get_sis_pqi_cap(softs);
if (ret) {		if (ret) {
DBG_ERR("Failed to get PQI Capabilities\n");		DBG_ERR("Failed to get PQI Capabilities\n");
goto err_out;		goto err_out;
}		}

		/* We need to allocate DMA memory here ,
		* Do any os specific DMA setup.
		*/
		ret = os_dma_setup(softs);
		if (ret) {
		DBG_ERR("Failed to Setup DMA\n");
		goto err_out;
		}

/* Init struct base addr */		/* Init struct base addr */
ret = pqisrc_init_struct_base(softs);		ret = pqisrc_init_struct_base(softs);
if (ret) {		if (ret) {
DBG_ERR("Failed to set init struct base addr\n");		DBG_ERR("Failed to set init struct base addr\n");
goto err_out;		goto err_dma;
}		}


DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
return ret;		return ret;

		err_dma:
		os_dma_destroy(softs);
err_out:		err_out:
DBG_FUNC("OUT failed\n");		DBG_FUNC("OUT failed\n");
return ret;		return ret;
}		}

/* Deallocate the resources used during SIS initialization */		/* Deallocate the resources used during SIS initialization */
void pqisrc_sis_uninit(pqisrc_softstate_t *softs)		void
		pqisrc_sis_uninit(pqisrc_softstate_t *softs)
{		{
DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

os_dma_mem_free(softs, &softs->err_buf_dma_mem);		os_dma_mem_free(softs, &softs->err_buf_dma_mem);

		os_dma_destroy(softs);
os_resource_free(softs);		os_resource_free(softs);
pqi_reset(softs);		pqi_reset(softs);


DBG_FUNC("OUT\n");		DBG_FUNC("OUT\n");
}		}

int pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit)		int
		pqisrc_sis_wait_for_db_bit_to_clear(pqisrc_softstate_t *softs, uint32_t bit)
{		{
int rcode = PQI_STATUS_SUCCESS;		int rcode = PQI_STATUS_SUCCESS;
uint32_t db_reg;		uint32_t db_reg;
uint32_t loop_cnt = 0;		uint32_t loop_cnt = 0;

DBG_FUNC("IN\n");		DBG_FUNC("IN\n");

while (1) {		while (1) {
Show All 21 Lines