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sys/arm64/rockchip/clk/rk3399_cru.c
| Show First 20 Lines • Show All 769 Lines • ▼ Show 20 Lines | |||||
| PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"}; | PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"}; | ||||
| PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"}; | PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"}; | ||||
| PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"}; | PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"}; | ||||
| PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"}; | PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"}; | ||||
| static struct rk_clk rk3399_clks[] = { | static struct rk_clk rk3399_clks[] = { | ||||
| /* External clocks */ | /* External clocks */ | ||||
| LINK("xin24m"), | LINK("xin24m"), | ||||
| FRATE(0, "xin32k", 32768), | LINK("xin32k"), | ||||
| FFACT(0, "xin12m", "xin24m", 1, 2), | FFACT(0, "xin12m", "xin24m", 1, 2), | ||||
| FRATE(0, "clkin_i2s", 0), | FRATE(0, "clkin_i2s", 0), | ||||
| FRATE(0, "pclkin_cif", 0), | FRATE(0, "pclkin_cif", 0), | ||||
| LINK("clk_usbphy0_480m"), | LINK("clk_usbphy0_480m"), | ||||
| LINK("clk_usbphy1_480m"), | LINK("clk_usbphy1_480m"), | ||||
| LINK("clkin_gmac"), | LINK("clkin_gmac"), | ||||
| FRATE(0, "clk_pcie_core_phy", 0), | FRATE(0, "clk_pcie_core_phy", 0), | ||||
| FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2), | FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2), | ||||
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