Differential D26976 Diff 88183 sys/arm64/arm64/gic_v3_reg.h

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sys/arm64/arm64/gic_v3_reg.h

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	/*			/*
	* Registers (v2/v3)			* Registers (v2/v3)
	*/			*/
	/* GICD_CTLR */			/* GICD_CTLR */
	#define GICD_CTLR_G1 (1 << 0)			#define GICD_CTLR_G1 (1 << 0)
	#define GICD_CTLR_G1A (1 << 1)			#define GICD_CTLR_G1A (1 << 1)
	#define GICD_CTLR_ARE_NS (1 << 4)			#define GICD_CTLR_ARE_NS (1 << 4)
				#define GICD_CTLR_DS (1 << 6)
				#define GICD_CTLR_E1NWF (1 << 7)
	#define GICD_CTLR_RWP (1 << 31)			#define GICD_CTLR_RWP (1 << 31)
	/* GICD_TYPER */			/* GICD_TYPER */
	#define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)			#define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)
				#define GICD_TYPER_SECURITYEXTN \
				(1 << 10)
				#define GICD_TYPER_DVIS (1 << 18)
				#define GICD_TYPER_LPIS (1 << 17)

	/*			/*
	* Registers (v3)			* Registers (v3)
	*/			*/
	#define GICD_IROUTER(n) (0x6000 + ((n) * 8))			#define GICD_IROUTER_BASE (0x6000)
				#define GICD_IROUTER(n) (GICD_IROUTER_BASE + ((n) * 8))
				#define GICD_IROUTER_IRM (1 << 31)

	#define GICD_PIDR4 0xFFD0			#define GICD_PIDR4 0xFFD0
	#define GICD_PIDR5 0xFFD4			#define GICD_PIDR5 0xFFD4
	#define GICD_PIDR6 0xFFD8			#define GICD_PIDR6 0xFFD8
	#define GICD_PIDR7 0xFFDC			#define GICD_PIDR7 0xFFDC
	#define GICD_PIDR0 0xFFE0			#define GICD_PIDR0 0xFFE0
	#define GICD_PIDR1 0xFFE4			#define GICD_PIDR1 0xFFE4
	#define GICD_PIDR2 0xFFE8			#define GICD_PIDR2 0xFFE8

	#define GICR_PIDR2_ARCH_SHIFT 4			#define GICR_PIDR2_ARCH_SHIFT 4
	#define GICR_PIDR2_ARCH_MASK 0xF0			#define GICR_PIDR2_ARCH_MASK 0xF0
	#define GICR_PIDR2_ARCH(x) \			#define GICR_PIDR2_ARCH(x) \
	(((x) & GICR_PIDR2_ARCH_MASK) >> GICR_PIDR2_ARCH_SHIFT)			(((x) & GICR_PIDR2_ARCH_MASK) >> GICR_PIDR2_ARCH_SHIFT)
	#define GICR_PIDR2_ARCH_GICv3 0x3			#define GICR_PIDR2_ARCH_GICv3 0x3
	#define GICR_PIDR2_ARCH_GICv4 0x4			#define GICR_PIDR2_ARCH_GICv4 0x4

	#define GICD_PIDR3 0xFFEC			#define GICD_PIDR3 0xFFEC

	/* Redistributor registers */			/* Redistributor registers */
	#define GICR_CTLR GICD_CTLR			#define GICR_CTLR GICD_CTLR
				#define GICR_CTLR_RWP (1 << 3)
				#define GICR_CTLR_UWP (1 << 31)
	#define GICR_CTLR_LPI_ENABLE (1 << 0)			#define GICR_CTLR_LPI_ENABLE (1 << 0)
				#define GICR_CTLR_DPG1NS (1 << 25)
				#define GICR_CTLR_DPG0 (1 << 24)

	#define GICR_PIDR2 GICD_PIDR2			#define GICR_PIDR2 GICD_PIDR2

	#define GICR_TYPER (0x0008)			#define GICR_TYPER (0x0008)
	#define GICR_TYPER_PLPIS (1 << 0)			#define GICR_TYPER_PLPIS (1 << 0)
	#define GICR_TYPER_VLPIS (1 << 1)			#define GICR_TYPER_VLPIS (1 << 1)
	#define GICR_TYPER_LAST (1 << 4)			#define GICR_TYPER_LAST (1 << 4)
	#define GICR_TYPER_CPUNUM_SHIFT (8)			#define GICR_TYPER_CPUNUM_SHIFT (8)
	#define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT)			#define GICR_TYPER_CPUNUM_MASK (0xFFFUL << GICR_TYPER_CPUNUM_SHIFT)
	#define GICR_TYPER_CPUNUM(x) \			#define GICR_TYPER_CPUNUM(x) \
	(((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT)			(((x) & GICR_TYPER_CPUNUM_MASK) >> GICR_TYPER_CPUNUM_SHIFT)
	#define GICR_TYPER_AFF_SHIFT (32)			#define GICR_TYPER_AFF_SHIFT (32)
				#define GICR_TYPER_AFF0(x) ((x >> GICR_TYPER_AFF_SHIFT) & 0xff)
				#define GICR_TYPER_AFF1(x) ((x >> (GICR_TYPER_AFF_SHIFT + 8)) & 0xff)
				#define GICR_TYPER_AFF2(x) ((x >> (GICR_TYPER_AFF_SHIFT + 16)) & 0xff)
				#define GICR_TYPER_AFF3(x) ((x >> (GICR_TYPER_AFF_SHIFT + 24)) & 0xff)

	#define GICR_WAKER (0x0014)			#define GICR_WAKER (0x0014)
	#define GICR_WAKER_PS (1 << 1) /* Processor sleep */			#define GICR_WAKER_PS (1 << 1) /* Processor sleep */
	#define GICR_WAKER_CA (1 << 2) /* Children asleep */			#define GICR_WAKER_CA (1 << 2) /* Children asleep */

	#define GICR_PROPBASER (0x0070)			#define GICR_PROPBASER (0x0070)
	#define GICR_PROPBASER_IDBITS_MASK 0x1FUL			#define GICR_PROPBASER_IDBITS_MASK 0x1FUL
	/*			/*
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	#define GICR_RESERVED_SIZE PAGE_SIZE_64K			#define GICR_RESERVED_SIZE PAGE_SIZE_64K

	#define GICR_IGROUPR0 (0x0080)			#define GICR_IGROUPR0 (0x0080)
	#define GICR_ISENABLER0 (0x0100)			#define GICR_ISENABLER0 (0x0100)
	#define GICR_ICENABLER0 (0x0180)			#define GICR_ICENABLER0 (0x0180)
	#define GICR_I_ENABLER_SGI_MASK (0x0000FFFF)			#define GICR_I_ENABLER_SGI_MASK (0x0000FFFF)
	#define GICR_I_ENABLER_PPI_MASK (0xFFFF0000)			#define GICR_I_ENABLER_PPI_MASK (0xFFFF0000)

				#define GICR_IPRIORITYR_BASE (0x0400)
	#define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn)			#define GICR_I_PER_IPRIORITYn (GICD_I_PER_IPRIORITYn)

				#define GICR_ICFGR0_BASE (0x0C00)
				#define GICR_ICFGR1_BASE (0x0C04)

	/* ITS registers */			/* ITS registers */
	#define GITS_PIDR2 GICR_PIDR2			#define GITS_PIDR2 GICR_PIDR2
	#define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK			#define GITS_PIDR2_ARCH_MASK GICR_PIDR2_ARCH_MASK
	#define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3			#define GITS_PIDR2_ARCH_GICv3 GICR_PIDR2_ARCH_GICv3
	#define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4			#define GITS_PIDR2_ARCH_GICv4 GICR_PIDR2_ARCH_GICv4

	#define GITS_CTLR (0x0000)			#define GITS_CTLR (0x0000)
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