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sys/riscv/riscv/exception.S
| Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines | .else | ||||
| sd t0, (TF_SP)(sp) | sd t0, (TF_SP)(sp) | ||||
| .endif | .endif | ||||
| li t0, 0 | li t0, 0 | ||||
| csrw sscratch, t0 | csrw sscratch, t0 | ||||
| csrr t0, sepc | csrr t0, sepc | ||||
| sd t0, (TF_SEPC)(sp) | sd t0, (TF_SEPC)(sp) | ||||
| csrr t0, sstatus | csrr t0, sstatus | ||||
| sd t0, (TF_SSTATUS)(sp) | sd t0, (TF_SSTATUS)(sp) | ||||
| .if \mode == 1 | |||||
| /* Disable user address access for supervisor mode exceptions. */ | |||||
| li t0, SSTATUS_SUM | |||||
| csrc sstatus, t0 | |||||
| .endif | |||||
jrtc27: You should be able to `li t0, SSTATUS_SUM; csrc sstatus, t0` | |||||
| csrr t0, stval | csrr t0, stval | ||||
| sd t0, (TF_STVAL)(sp) | sd t0, (TF_STVAL)(sp) | ||||
| csrr t0, scause | csrr t0, scause | ||||
| sd t0, (TF_SCAUSE)(sp) | sd t0, (TF_SCAUSE)(sp) | ||||
| .endm | .endm | ||||
| .macro load_registers mode | .macro load_registers mode | ||||
| ld t0, (TF_SSTATUS)(sp) | ld t0, (TF_SSTATUS)(sp) | ||||
| ▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines | |||||
You should be able to li t0, SSTATUS_SUM; csrc sstatus, t0