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usr.sbin/bhyve/pci_emul.h
Show All 36 Lines | |||||
#include <sys/nv.h> | #include <sys/nv.h> | ||||
#include <sys/_pthreadtypes.h> | #include <sys/_pthreadtypes.h> | ||||
#include <dev/pci/pcireg.h> | #include <dev/pci/pcireg.h> | ||||
#include <assert.h> | #include <assert.h> | ||||
#define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ | #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ | ||||
#define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1) | |||||
#define PCI_ROM_IDX (PCI_BARMAX + 1) | |||||
struct vmctx; | struct vmctx; | ||||
struct pci_devinst; | struct pci_devinst; | ||||
struct memory_region; | struct memory_region; | ||||
struct vm_snapshot_meta; | struct vm_snapshot_meta; | ||||
struct pci_devemu { | struct pci_devemu { | ||||
char *pe_emu; /* Name of device emulation */ | char *pe_emu; /* Name of device emulation */ | ||||
Show All 18 Lines | struct pci_devemu { | ||||
/* BAR read/write callbacks */ | /* BAR read/write callbacks */ | ||||
void (*pe_barwrite)(struct vmctx *ctx, int vcpu, | void (*pe_barwrite)(struct vmctx *ctx, int vcpu, | ||||
struct pci_devinst *pi, int baridx, | struct pci_devinst *pi, int baridx, | ||||
uint64_t offset, int size, uint64_t value); | uint64_t offset, int size, uint64_t value); | ||||
uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, | uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, | ||||
struct pci_devinst *pi, int baridx, | struct pci_devinst *pi, int baridx, | ||||
uint64_t offset, int size); | uint64_t offset, int size); | ||||
void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, | int (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, int baridx, | ||||
int baridx, int enabled, uint64_t address); | int enabled, uint64_t address); | ||||
/* Save/restore device state */ | /* Save/restore device state */ | ||||
int (*pe_snapshot)(struct vm_snapshot_meta *meta); | int (*pe_snapshot)(struct vm_snapshot_meta *meta); | ||||
int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi); | int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi); | ||||
int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi); | int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi); | ||||
}; | }; | ||||
#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); | #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); | ||||
enum pcibar_type { | enum pcibar_type { | ||||
PCIBAR_NONE, | PCIBAR_NONE, | ||||
PCIBAR_IO, | PCIBAR_IO, | ||||
PCIBAR_MEM32, | PCIBAR_MEM32, | ||||
PCIBAR_MEM64, | PCIBAR_MEM64, | ||||
PCIBAR_MEMHI64 | PCIBAR_MEMHI64, | ||||
PCIBAR_ROM, | |||||
}; | }; | ||||
struct pcibar { | struct pcibar { | ||||
enum pcibar_type type; /* io or memory */ | enum pcibar_type type; /* io or memory */ | ||||
uint64_t size; | uint64_t size; | ||||
uint64_t addr; | uint64_t addr; | ||||
uint8_t lobits; | |||||
}; | }; | ||||
#define PI_NAMESZ 40 | #define PI_NAMESZ 40 | ||||
struct msix_table_entry { | struct msix_table_entry { | ||||
uint64_t addr; | uint64_t addr; | ||||
uint32_t msg_data; | uint32_t msg_data; | ||||
uint32_t vector_control; | uint32_t vector_control; | ||||
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines | struct { | ||||
struct msix_table_entry *table; /* allocated at runtime */ | struct msix_table_entry *table; /* allocated at runtime */ | ||||
void *pba_page; | void *pba_page; | ||||
int pba_page_offset; | int pba_page_offset; | ||||
} pi_msix; | } pi_msix; | ||||
void *pi_arg; /* devemu-private data */ | void *pi_arg; /* devemu-private data */ | ||||
u_char pi_cfgdata[PCI_REGMAX + 1]; | u_char pi_cfgdata[PCI_REGMAX + 1]; | ||||
struct pcibar pi_bar[PCI_BARMAX + 1]; | /* ROM is handled like a BAR */ | ||||
struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1]; | |||||
}; | }; | ||||
struct msicap { | struct msicap { | ||||
uint8_t capid; | uint8_t capid; | ||||
uint8_t nextptr; | uint8_t nextptr; | ||||
uint16_t msgctrl; | uint16_t msgctrl; | ||||
uint32_t addrlo; | uint32_t addrlo; | ||||
uint32_t addrhi; | uint32_t addrhi; | ||||
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines |