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usr.sbin/bhyve/pci_emul.h
| Show First 20 Lines • Show All 70 Lines • ▼ Show 20 Lines | struct pci_devemu { | ||||
| /* BAR read/write callbacks */ | /* BAR read/write callbacks */ | ||||
| void (*pe_barwrite)(struct vmctx *ctx, int vcpu, | void (*pe_barwrite)(struct vmctx *ctx, int vcpu, | ||||
| struct pci_devinst *pi, int baridx, | struct pci_devinst *pi, int baridx, | ||||
| uint64_t offset, int size, uint64_t value); | uint64_t offset, int size, uint64_t value); | ||||
| uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, | uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, | ||||
| struct pci_devinst *pi, int baridx, | struct pci_devinst *pi, int baridx, | ||||
| uint64_t offset, int size); | uint64_t offset, int size); | ||||
| void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, | int (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, int baridx, | ||||
| int baridx, int enabled, uint64_t address); | int enabled, uint64_t address); | ||||
| /* Save/restore device state */ | /* Save/restore device state */ | ||||
| int (*pe_snapshot)(struct vm_snapshot_meta *meta); | int (*pe_snapshot)(struct vm_snapshot_meta *meta); | ||||
| int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi); | int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi); | ||||
| int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi); | int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi); | ||||
| }; | }; | ||||
| #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); | #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); | ||||
| enum pcibar_type { | enum pcibar_type { | ||||
| PCIBAR_NONE, | PCIBAR_NONE, | ||||
| PCIBAR_IO, | PCIBAR_IO, | ||||
| PCIBAR_MEM32, | PCIBAR_MEM32, | ||||
| PCIBAR_MEM64, | PCIBAR_MEM64, | ||||
| PCIBAR_MEMHI64 | PCIBAR_MEMHI64 | ||||
| }; | }; | ||||
| struct pcibar { | struct pcibar { | ||||
| enum pcibar_type type; /* io or memory */ | enum pcibar_type type; /* io or memory */ | ||||
| uint64_t size; | uint64_t size; | ||||
| uint64_t addr; | uint64_t addr; | ||||
| uint8_t lobits; | |||||
| }; | }; | ||||
| #define PI_NAMESZ 40 | #define PI_NAMESZ 40 | ||||
| struct msix_table_entry { | struct msix_table_entry { | ||||
| uint64_t addr; | uint64_t addr; | ||||
| uint32_t msg_data; | uint32_t msg_data; | ||||
| uint32_t vector_control; | uint32_t vector_control; | ||||
| ▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines | |||||
| typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, | typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, | ||||
| int ioapic_irq, void *arg); | int ioapic_irq, void *arg); | ||||
| int init_pci(struct vmctx *ctx); | int init_pci(struct vmctx *ctx); | ||||
| void pci_callback(void); | void pci_callback(void); | ||||
| int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, | int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, | ||||
| enum pcibar_type type, uint64_t size); | enum pcibar_type type, uint64_t size); | ||||
| uint64_t pci_emul_alloc_gsm(uint64_t size); | |||||
| int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); | int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); | ||||
| int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); | int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); | ||||
| void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, | void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, | ||||
| uint32_t val, uint8_t capoff, int capid); | uint32_t val, uint8_t capoff, int capid); | ||||
| void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); | void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); | ||||
| void pci_generate_msi(struct pci_devinst *pi, int msgnum); | void pci_generate_msi(struct pci_devinst *pi, int msgnum); | ||||
| void pci_generate_msix(struct pci_devinst *pi, int msgnum); | void pci_generate_msix(struct pci_devinst *pi, int msgnum); | ||||
| void pci_lintr_assert(struct pci_devinst *pi); | void pci_lintr_assert(struct pci_devinst *pi); | ||||
| ▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines | |||||
| static __inline uint32_t | static __inline uint32_t | ||||
| pci_get_cfgdata32(struct pci_devinst *pi, int offset) | pci_get_cfgdata32(struct pci_devinst *pi, int offset) | ||||
| { | { | ||||
| assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); | assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); | ||||
| return (*(uint32_t *)(pi->pi_cfgdata + offset)); | return (*(uint32_t *)(pi->pi_cfgdata + offset)); | ||||
| } | } | ||||
| #endif /* _PCI_EMUL_H_ */ | #endif /* _PCI_EMUL_H_ */ | ||||
corvink: Changing this function would enable GPU-Passthrough of dedicated graphics to a Windows VM:
```… | |||||
Changing this function would enable GPU-Passthrough of dedicated graphics to a Windows VM:
static __inline int is_passthru(struct pci_devinst *pi) { return ((strcmp(pi->pi_d->pe_emu, "passthru") == 0) || (strcmp(pi->pi_d->pe_emu, "gvt-d") == 0)); }