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lib/msun/aarch64/fenv.h
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#define _FENV_H_ | #define _FENV_H_ | ||||
#include <sys/_types.h> | #include <sys/_types.h> | ||||
#ifndef __fenv_static | #ifndef __fenv_static | ||||
#define __fenv_static static | #define __fenv_static static | ||||
#endif | #endif | ||||
/* The high 32 bits contain fpcr, low 32 contain fpsr. */ | |||||
typedef __uint64_t fenv_t; | typedef __uint64_t fenv_t; | ||||
typedef __uint64_t fexcept_t; | typedef __uint64_t fexcept_t; | ||||
/* Exception flags */ | /* Exception flags */ | ||||
#define FE_INVALID 0x00000001 | #define FE_INVALID 0x00000001 | ||||
#define FE_DIVBYZERO 0x00000002 | #define FE_DIVBYZERO 0x00000002 | ||||
#define FE_OVERFLOW 0x00000004 | #define FE_OVERFLOW 0x00000004 | ||||
#define FE_UNDERFLOW 0x00000008 | #define FE_UNDERFLOW 0x00000008 | ||||
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | fesetround(int __round) | ||||
__r |= __round << _ROUND_SHIFT; | __r |= __round << _ROUND_SHIFT; | ||||
__msr_fpcr(__r); | __msr_fpcr(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fegetenv(fenv_t *__envp) | fegetenv(fenv_t *__envp) | ||||
{ | { | ||||
fenv_t __r; | __uint64_t fpcr; | ||||
__uint64_t fpsr; | |||||
__mrs_fpcr(__r); | __mrs_fpcr(fpcr); | ||||
*__envp = __r & _ENABLE_MASK; | __mrs_fpsr(fpsr); | ||||
*__envp = fpsr | (fpcr << 32); | |||||
__mrs_fpsr(__r); | |||||
*__envp |= __r & (FE_ALL_EXCEPT | (_ROUND_MASK << _ROUND_SHIFT)); | |||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
feholdexcept(fenv_t *__envp) | feholdexcept(fenv_t *__envp) | ||||
{ | { | ||||
fenv_t __r; | fenv_t __r; | ||||
__mrs_fpcr(__r); | __mrs_fpcr(__r); | ||||
*__envp = __r & _ENABLE_MASK; | *__envp = __r << 32; | ||||
__r &= ~(_ENABLE_MASK); | __r &= ~(_ENABLE_MASK); | ||||
__msr_fpcr(__r); | __msr_fpcr(__r); | ||||
__mrs_fpsr(__r); | __mrs_fpsr(__r); | ||||
*__envp |= __r & (FE_ALL_EXCEPT | (_ROUND_MASK << _ROUND_SHIFT)); | *__envp |= (__uint32_t)__r; | ||||
__r &= ~(_ENABLE_MASK); | __r &= ~(_ENABLE_MASK); | ||||
__msr_fpsr(__r); | __msr_fpsr(__r); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
fesetenv(const fenv_t *__envp) | fesetenv(const fenv_t *__envp) | ||||
{ | { | ||||
__msr_fpcr((*__envp) & _ENABLE_MASK); | __msr_fpcr((*__envp) >> 32); | ||||
__msr_fpsr((*__envp) & (FE_ALL_EXCEPT | (_ROUND_MASK << _ROUND_SHIFT))); | __msr_fpsr((fenv_t)(__uint32_t)*__envp); | ||||
return (0); | return (0); | ||||
} | } | ||||
__fenv_static inline int | __fenv_static inline int | ||||
feupdateenv(const fenv_t *__envp) | feupdateenv(const fenv_t *__envp) | ||||
{ | { | ||||
fexcept_t __r; | fexcept_t __r; | ||||
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