Differential D28640 Diff 84514 sys/dev/ice/ice_adminq_cmd.h

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sys/dev/ice/ice_adminq_cmd.h

/* SPDX-License-Identifier: BSD-3-Clause */		/* SPDX-License-Identifier: BSD-3-Clause */
/* Copyright (c) 2020, Intel Corporation		/* Copyright (c) 2021, Intel Corporation
* All rights reserved.		* All rights reserved.
*		*
* Redistribution and use in source and binary forms, with or without		* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:		* modification, are permitted provided that the following conditions are met:
*		*
* 1. Redistributions of source code must retain the above copyright notice,		* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.		* this list of conditions and the following disclaimer.
*		*
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#define ICE_AQC_CAPS_CEM 0x00F2		#define ICE_AQC_CAPS_CEM 0x00F2
#define ICE_AQC_CAPS_IWARP 0x0051		#define ICE_AQC_CAPS_IWARP 0x0051
#define ICE_AQC_CAPS_LED 0x0061		#define ICE_AQC_CAPS_LED 0x0061
#define ICE_AQC_CAPS_SDP 0x0062		#define ICE_AQC_CAPS_SDP 0x0062
#define ICE_AQC_CAPS_WR_CSR_PROT 0x0064		#define ICE_AQC_CAPS_WR_CSR_PROT 0x0064
#define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073		#define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073
#define ICE_AQC_CAPS_SKU 0x0074		#define ICE_AQC_CAPS_SKU 0x0074
#define ICE_AQC_CAPS_PORT_MAP 0x0075		#define ICE_AQC_CAPS_PORT_MAP 0x0075
		#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
#define ICE_AQC_CAPS_NVM_MGMT 0x0080		#define ICE_AQC_CAPS_NVM_MGMT 0x0080

u8 major_ver;		u8 major_ver;
u8 minor_ver;		u8 minor_ver;
/* Number of resources described by this capability */		/* Number of resources described by this capability */
__le32 number;		__le32 number;
/* Only meaningful for some types of resources */		/* Only meaningful for some types of resources */
__le32 logical_id;		__le32 logical_id;
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#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)		#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)		#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)		#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
u8 link_cfg_err;		u8 link_cfg_err;
#define ICE_AQ_LINK_CFG_ERR BIT(0)		#define ICE_AQ_LINK_CFG_ERR BIT(0)
#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)		#define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2)
#define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)		#define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3)
#define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)		#define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4)
		#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
u8 link_info;		u8 link_info;
#define ICE_AQ_LINK_UP BIT(0) /* Link Status */		#define ICE_AQ_LINK_UP BIT(0) /* Link Status */
#define ICE_AQ_LINK_FAULT BIT(1)		#define ICE_AQ_LINK_FAULT BIT(1)
#define ICE_AQ_LINK_FAULT_TX BIT(2)		#define ICE_AQ_LINK_FAULT_TX BIT(2)
#define ICE_AQ_LINK_FAULT_RX BIT(3)		#define ICE_AQ_LINK_FAULT_RX BIT(3)
#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)		#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */		#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
#define ICE_AQ_MEDIA_AVAILABLE BIT(6)		#define ICE_AQ_MEDIA_AVAILABLE BIT(6)
Show All 31 Lines	#define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0)
/* Pacing Config */		/* Pacing Config */
#define ICE_AQ_CFG_PACING_S 3		#define ICE_AQ_CFG_PACING_S 3
#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)		#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)		#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
#define ICE_AQ_CFG_PACING_TYPE_AVG 0		#define ICE_AQ_CFG_PACING_TYPE_AVG 0
#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M		#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
/* External Device Power Ability */		/* External Device Power Ability */
u8 power_desc;		u8 power_desc;
#define ICE_AQ_PWR_CLASS_M 0x3		#define ICE_AQ_PWR_CLASS_M 0x3F
#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0		#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
#define ICE_AQ_LINK_PWR_BASET_HIGH 1		#define ICE_AQ_LINK_PWR_BASET_HIGH 1
#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0		#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1		#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2		#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3		#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
__le16 link_speed;		__le16 link_speed;
#define ICE_AQ_LINK_SPEED_M 0x7FF		#define ICE_AQ_LINK_SPEED_M 0x7FF
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/* Read/Write MDIO (direct, 0x06E4/0x06E5) */		/* Read/Write MDIO (direct, 0x06E4/0x06E5) */
struct ice_aqc_mdio {		struct ice_aqc_mdio {
struct ice_aqc_link_topo_addr topo_addr;		struct ice_aqc_link_topo_addr topo_addr;
u8 mdio_device_addr;		u8 mdio_device_addr;
#define ICE_AQC_MDIO_DEV_S 0		#define ICE_AQC_MDIO_DEV_S 0
#define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S)		#define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S)
#define ICE_AQC_MDIO_CLAUSE_22 BIT(5)		#define ICE_AQC_MDIO_CLAUSE_22 BIT(5)
#define ICE_AQC_MDIO_CLAUSE_45 BIT(6)		#define ICE_AQC_MDIO_CLAUSE_45 BIT(6)
u8 rsvd;		u8 mdio_bus_address;
		#define ICE_AQC_MDIO_BUS_ADDR_S 0
		#define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S)
__le16 offset;		__le16 offset;
__le16 data; /* Input in write cmd, output in read cmd. */		__le16 data; /* Input in write cmd, output in read cmd. */
u8 rsvd1[4];		u8 rsvd1[4];
};		};

/* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */		/* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */
struct ice_aqc_gpio_by_func {		struct ice_aqc_gpio_by_func {
struct ice_aqc_link_topo_addr topo_addr;		struct ice_aqc_link_topo_addr topo_addr;
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#define ICE_AQC_SFF_EEPROM_BANK_S 0		#define ICE_AQC_SFF_EEPROM_BANK_S 0
#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)		#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
#define ICE_AQC_SFF_EEPROM_PAGE_S 8		#define ICE_AQC_SFF_EEPROM_PAGE_S 8
#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)		#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
__le32 addr_high;		__le32 addr_high;
__le32 addr_low;		__le32 addr_low;
};		};

		/* SW Set GPIO command (indirect 0x6EF)
		* SW Get GPIO command (indirect 0x6F0)
		*/
		struct ice_aqc_sw_gpio {
		__le16 gpio_ctrl_handle;
		#define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0
		#define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
		u8 gpio_num;
		#define ICE_AQC_SW_GPIO_NUMBER_S 0
		#define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
		u8 gpio_params;
		#define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1)
		#define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0)
		u8 rsvd[12];
		};

/* NVM Read command (indirect 0x0701)		/* NVM Read command (indirect 0x0701)
* NVM Erase commands (direct 0x0702)		* NVM Erase commands (direct 0x0702)
* NVM Write commands (indirect 0x0703)		* NVM Write commands (indirect 0x0703)
* NVM Write Activate commands (direct 0x0707)		* NVM Write Activate commands (direct 0x0707)
* NVM Shadow RAM Dump commands (direct 0x0707)		* NVM Shadow RAM Dump commands (direct 0x0707)
*/		*/
struct ice_aqc_nvm {		struct ice_aqc_nvm {
#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF		#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
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#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)		#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */		#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)		#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)		#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)		#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */		#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)		#define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3)
#define ICE_AQC_NVM_FLASH_ONLY BIT(7)		#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
		#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */
		#define ICE_AQC_NVM_PERST_FLAG 1
		#define ICE_AQC_NVM_EMPR_FLAG 2
__le16 module_typeid;		__le16 module_typeid;
__le16 length;		__le16 length;
#define ICE_AQC_NVM_ERASE_LEN 0xFFFF		#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
__le32 addr_high;		__le32 addr_high;
__le32 addr_low;		__le32 addr_low;
};		};

/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */		/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
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#define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */		#define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */

#define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129		#define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129
#define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */		#define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */
#define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)		#define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0)
#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */		#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */		#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */

/* The result of netlist NVM read comes in a TLV format. The actual data		#define ICE_AQC_NVM_MINSREV_MOD_ID 0x130
* (netlist header) starts from word offset 1 (byte 2). The FW strips
* out the type field from the TLV header so all the netlist fields		/* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the
* should adjust their offset value by 1 word (2 bytes) in order to map		* type field is excluded from the section when reading and writing from
* their correct location.		* a module using the module_typeid field with these AQ commands.
*/		*/
#define ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID 0x11B		struct ice_aqc_nvm_minsrev {
#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET 1		__le16 length;
#define ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN 2 /* In bytes */		__le16 validity;
#define ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET 2		#define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0)
#define ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN 2 /* In bytes */		#define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1)
#define ICE_AQC_NVM_NETLIST_NODE_COUNT_M MAKEMASK(0x3FF, 0)		__le16 nvm_minsrev_l;
#define ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET 5		__le16 nvm_minsrev_h;
#define ICE_AQC_NVM_NETLIST_ID_BLK_LEN 0x30 /* In words */		__le16 orom_minsrev_l;
		__le16 orom_minsrev_h;
		};

/* netlist ID block field offsets (word offsets) */
#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW 2
#define ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH 3
#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW 4
#define ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH 5
#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW 6
#define ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH 7
#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW 8
#define ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH 9
#define ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH 0xA
#define ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER 0x2F

/* Used for 0x0704 as well as for 0x0705 commands */		/* Used for 0x0704 as well as for 0x0705 commands */
struct ice_aqc_nvm_cfg {		struct ice_aqc_nvm_cfg {
u8 cmd_flags;		u8 cmd_flags;
#define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)		#define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0)
#define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)		#define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1)
#define ICE_AQC_ANVM_NEW_CFG BIT(2)		#define ICE_AQC_ANVM_NEW_CFG BIT(2)
u8 reserved;		u8 reserved;
__le16 count;		__le16 count;
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#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)		#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)		#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
u8 rsvd;		u8 rsvd;
__le16 checksum; /* Used only by response */		__le16 checksum; /* Used only by response */
#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA		#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
u8 rsvd2[12];		u8 rsvd2[12];
};		};

/**		/*
* Send to PF command (indirect 0x0801) ID is only used by PF		* Send to PF command (indirect 0x0801) ID is only used by PF
*		*
* Send to VF command (indirect 0x0802) ID is only used by PF		* Send to VF command (indirect 0x0802) ID is only used by PF
*		*
*/		*/
struct ice_aqc_pf_vf_msg {		struct ice_aqc_pf_vf_msg {
__le32 id;		__le32 id;
u32 reserved;		u32 reserved;
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struct ice_pkg_ver {		struct ice_pkg_ver {
u8 major;		u8 major;
u8 minor;		u8 minor;
u8 update;		u8 update;
u8 draft;		u8 draft;
};		};

#define ICE_PKG_NAME_SIZE 32		#define ICE_PKG_NAME_SIZE 32
		#define ICE_SEG_ID_SIZE 28
#define ICE_SEG_NAME_SIZE 28		#define ICE_SEG_NAME_SIZE 28

struct ice_aqc_get_pkg_info {		struct ice_aqc_get_pkg_info {
struct ice_pkg_ver ver;		struct ice_pkg_ver ver;
char name[ICE_SEG_NAME_SIZE];		char name[ICE_SEG_NAME_SIZE];
__le32 track_id;		__le32 track_id;
u8 is_in_nvm;		u8 is_in_nvm;
u8 is_active;		u8 is_active;
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struct ice_aqc_set_health_status_config {		struct ice_aqc_set_health_status_config {
u8 event_source;		u8 event_source;
#define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)		#define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0)
#define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)		#define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1)
#define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)		#define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2)
u8 reserved[15];		u8 reserved[15];
};		};

		#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101
		#define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102
		#define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103
		#define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104
		#define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105
		#define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
		#define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
		#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
		#define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
		#define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
		#define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
		#define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F
		#define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110
		#define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111
		#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112
		#define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113
		#define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114
		#define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115
		#define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116
		#define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117
		#define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500
		#define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501
		#define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502
		#define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503
		#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
		#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
		#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
		#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509

/* Get Health Status codes (indirect 0xFF21) */		/* Get Health Status codes (indirect 0xFF21) */
struct ice_aqc_get_supported_health_status_codes {		struct ice_aqc_get_supported_health_status_codes {
__le16 health_code_count;		__le16 health_code_count;
u8 reserved[6];		u8 reserved[6];
__le32 addr_high;		__le32 addr_high;
__le32 addr_low;		__le32 addr_low;
};		};

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};		};

/**		/**
* struct ice_aq_desc - Admin Queue (AQ) descriptor		* struct ice_aq_desc - Admin Queue (AQ) descriptor
* @flags: ICE_AQ_FLAG_* flags		* @flags: ICE_AQ_FLAG_* flags
* @opcode: AQ command opcode		* @opcode: AQ command opcode
* @datalen: length in bytes of indirect/external data buffer		* @datalen: length in bytes of indirect/external data buffer
* @retval: return value from firmware		* @retval: return value from firmware
* @cookie_h: opaque data high-half		* @cookie_high: opaque data high-half
* @cookie_l: opaque data low-half		* @cookie_low: opaque data low-half
* @params: command-specific parameters		* @params: command-specific parameters
*		*
* Descriptor format for commands the driver posts on the Admin Transmit Queue		* Descriptor format for commands the driver posts on the Admin Transmit Queue
* (ATQ). The firmware writes back onto the command descriptor and returns		* (ATQ). The firmware writes back onto the command descriptor and returns
* the result of the command. Asynchronous events that are not an immediate		* the result of the command. Asynchronous events that are not an immediate
* result of the command are written to the Admin Receive Queue (ARQ) using		* result of the command are written to the Admin Receive Queue (ARQ) using
* the same descriptor format. Descriptors are in little-endian notation with		* the same descriptor format. Descriptors are in little-endian notation with
* 32-bit words.		* 32-bit words.
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines	enum ice_adminq_opc {
ice_aqc_opc_get_gpio_by_func = 0x06E7,		ice_aqc_opc_get_gpio_by_func = 0x06E7,
ice_aqc_opc_set_led = 0x06E8,		ice_aqc_opc_set_led = 0x06E8,
ice_aqc_opc_set_port_id_led = 0x06E9,		ice_aqc_opc_set_port_id_led = 0x06E9,
ice_aqc_opc_get_port_options = 0x06EA,		ice_aqc_opc_get_port_options = 0x06EA,
ice_aqc_opc_set_port_option = 0x06EB,		ice_aqc_opc_set_port_option = 0x06EB,
ice_aqc_opc_set_gpio = 0x06EC,		ice_aqc_opc_set_gpio = 0x06EC,
ice_aqc_opc_get_gpio = 0x06ED,		ice_aqc_opc_get_gpio = 0x06ED,
ice_aqc_opc_sff_eeprom = 0x06EE,		ice_aqc_opc_sff_eeprom = 0x06EE,
		ice_aqc_opc_sw_set_gpio = 0x06EF,
		ice_aqc_opc_sw_get_gpio = 0x06F0,

/* NVM commands */		/* NVM commands */
ice_aqc_opc_nvm_read = 0x0701,		ice_aqc_opc_nvm_read = 0x0701,
ice_aqc_opc_nvm_erase = 0x0702,		ice_aqc_opc_nvm_erase = 0x0702,
ice_aqc_opc_nvm_write = 0x0703,		ice_aqc_opc_nvm_write = 0x0703,
ice_aqc_opc_nvm_cfg_read = 0x0704,		ice_aqc_opc_nvm_cfg_read = 0x0704,
ice_aqc_opc_nvm_cfg_write = 0x0705,		ice_aqc_opc_nvm_cfg_write = 0x0705,
ice_aqc_opc_nvm_checksum = 0x0706,		ice_aqc_opc_nvm_checksum = 0x0706,
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