Differential D28415 Diff 84092 sys/arm64/include/armreg.h

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sys/arm64/include/armreg.h

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	#define DBG_BCR_HMC (0x1 << DBG_BCR_HMC_SHIFT)			#define DBG_BCR_HMC (0x1 << DBG_BCR_HMC_SHIFT)
	#define DBG_BCR_SSC_SHIFT 14			#define DBG_BCR_SSC_SHIFT 14
	#define DBG_BCR_SSC (0x3 << DBG_BCR_SSC_SHIFT)			#define DBG_BCR_SSC (0x3 << DBG_BCR_SSC_SHIFT)
	#define DBG_BCR_LBN_SHIFT 16			#define DBG_BCR_LBN_SHIFT 16
	#define DBG_BCR_LBN (0xf << DBG_BCR_LBN_SHIFT)			#define DBG_BCR_LBN (0xf << DBG_BCR_LBN_SHIFT)
	#define DBG_BCR_BT_SHIFT 20			#define DBG_BCR_BT_SHIFT 20
	#define DBG_BCR_BT (0xf << DBG_BCR_BT_SHIFT)			#define DBG_BCR_BT (0xf << DBG_BCR_BT_SHIFT)

				/* Debug Watchpoint Control Registers */
				#define DBG_WCR_EN 0x1
				#define DBG_WCR_PAC_SHIFT 1
				#define DBG_WCR_PAC (0x3 << DBG_WCR_PAC_SHIFT)
				#define DBG_WCR_PAC_EL1 (0x1 << DBG_WCR_PAC_SHIFT)
				#define DBG_WCR_PAC_EL0 (0x2 << DBG_WCR_PAC_SHIFT)
				#define DBG_WCR_LSC_SHIFT 3
				#define DBG_WCR_LSC (0x3 << DBG_WCR_LSC_SHIFT)
				#define DBG_WCR_BAS_SHIFT 5
				#define DBG_WCR_BAS (0xff << DBG_WCR_BAS_SHIFT)
				#define DBG_WCR_BAS_MASK DBG_WCR_BAS
				#define DBG_WCR_HMC_SHIFT 13
				#define DBG_WCR_HMC (0x1 << DBG_WCR_HMC_SHIFT)
				#define DBG_WCR_SSC_SHIFT 14
				#define DBG_WCR_SSC (0x3 << DBG_WCR_SSC_SHIFT)
				#define DBG_WCR_LBN_SHIFT 16
				#define DBG_WCR_LBN (0xf << DBG_WCR_LBN_SHIFT)
				#define DBG_WCR_WT_SHIFT 20
				#define DBG_WCR_WT (0x1 << DBG_WCR_WT_SHIFT)
				#define DBG_WCR_MASK_SHIFT 24
				#define DBG_WCR_MASK (0x1f << DBG_WCR_MASK_SHIFT)

	/* Perfomance Monitoring Counters */			/* Perfomance Monitoring Counters */
	#define PMCR_E (1 << 0) /* Enable all counters */			#define PMCR_E (1 << 0) /* Enable all counters */
	#define PMCR_P (1 << 1) /* Reset all counters */			#define PMCR_P (1 << 1) /* Reset all counters */
	#define PMCR_C (1 << 2) /* Clock counter reset */			#define PMCR_C (1 << 2) /* Clock counter reset */
	#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */			#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
	#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */			#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
	#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/			#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
	#define PMCR_LC (1 << 6) /* Long cycle count enable */			#define PMCR_LC (1 << 6) /* Long cycle count enable */
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