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sys/dev/ice/ice_common.c
/* SPDX-License-Identifier: BSD-3-Clause */ | /* SPDX-License-Identifier: BSD-3-Clause */ | ||||
/* Copyright (c) 2020, Intel Corporation | /* Copyright (c) 2021, Intel Corporation | ||||
* All rights reserved. | * All rights reserved. | ||||
* | * | ||||
* Redistribution and use in source and binary forms, with or without | * Redistribution and use in source and binary forms, with or without | ||||
* modification, are permitted provided that the following conditions are met: | * modification, are permitted provided that the following conditions are met: | ||||
* | * | ||||
* 1. Redistributions of source code must retain the above copyright notice, | * 1. Redistributions of source code must retain the above copyright notice, | ||||
* this list of conditions and the following disclaimer. | * this list of conditions and the following disclaimer. | ||||
* | * | ||||
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines | cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << | ||||
ICE_AQC_LINK_TOPO_NODE_CTX_S); | ICE_AQC_LINK_TOPO_NODE_CTX_S); | ||||
/* set node type */ | /* set node type */ | ||||
cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); | cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); | ||||
return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); | return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); | ||||
} | } | ||||
/* | /** | ||||
* ice_is_media_cage_present | * ice_is_media_cage_present | ||||
* @pi: port information structure | * @pi: port information structure | ||||
* | * | ||||
* Returns true if media cage is present, else false. If no cage, then | * Returns true if media cage is present, else false. If no cage, then | ||||
* media type is backplane or BASE-T. | * media type is backplane or BASE-T. | ||||
*/ | */ | ||||
static bool ice_is_media_cage_present(struct ice_port_info *pi) | static bool ice_is_media_cage_present(struct ice_port_info *pi) | ||||
{ | { | ||||
▲ Show 20 Lines • Show All 422 Lines • ▼ Show 20 Lines | |||||
/** | /** | ||||
* ice_print_rollback_msg - print FW rollback message | * ice_print_rollback_msg - print FW rollback message | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
*/ | */ | ||||
void ice_print_rollback_msg(struct ice_hw *hw) | void ice_print_rollback_msg(struct ice_hw *hw) | ||||
{ | { | ||||
char nvm_str[ICE_NVM_VER_LEN] = { 0 }; | char nvm_str[ICE_NVM_VER_LEN] = { 0 }; | ||||
struct ice_nvm_info *nvm = &hw->nvm; | |||||
struct ice_orom_info *orom; | struct ice_orom_info *orom; | ||||
struct ice_nvm_info *nvm; | |||||
orom = &nvm->orom; | orom = &hw->flash.orom; | ||||
nvm = &hw->flash.nvm; | |||||
SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", | SNPRINTF(nvm_str, sizeof(nvm_str), "%x.%02x 0x%x %d.%d.%d", | ||||
nvm->major_ver, nvm->minor_ver, nvm->eetrack, orom->major, | nvm->major, nvm->minor, nvm->eetrack, orom->major, | ||||
orom->build, orom->patch); | orom->build, orom->patch); | ||||
ice_warn(hw, | ice_warn(hw, | ||||
"Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", | "Firmware rollback mode detected. Current version is NVM: %s, FW: %d.%d. Device may exhibit limited functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware rollback mode\n", | ||||
nvm_str, hw->fw_maj_ver, hw->fw_min_ver); | nvm_str, hw->fw_maj_ver, hw->fw_min_ver); | ||||
} | } | ||||
/** | /** | ||||
* ice_init_hw - main hardware initialization routine | * ice_init_hw - main hardware initialization routine | ||||
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines | if (!pcaps) { | ||||
goto err_unroll_sched; | goto err_unroll_sched; | ||||
} | } | ||||
/* Initialize port_info struct with PHY capabilities */ | /* Initialize port_info struct with PHY capabilities */ | ||||
status = ice_aq_get_phy_caps(hw->port_info, false, | status = ice_aq_get_phy_caps(hw->port_info, false, | ||||
ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); | ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL); | ||||
ice_free(hw, pcaps); | ice_free(hw, pcaps); | ||||
if (status) | if (status) | ||||
ice_debug(hw, ICE_DBG_PHY, "%s: Get PHY capabilities failed, continuing anyway\n", | ice_debug(hw, ICE_DBG_PHY, "Get PHY capabilities failed, continuing anyway\n"); | ||||
__func__); | |||||
/* Initialize port_info struct with link information */ | /* Initialize port_info struct with link information */ | ||||
status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); | status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); | ||||
if (status) | if (status) | ||||
goto err_unroll_sched; | goto err_unroll_sched; | ||||
/* need a valid SW entry point to build a Tx tree */ | /* need a valid SW entry point to build a Tx tree */ | ||||
if (!hw->sw_entry_point_layer) { | if (!hw->sw_entry_point_layer) { | ||||
ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); | ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n"); | ||||
Show All 27 Lines | enum ice_status ice_init_hw(struct ice_hw *hw) | ||||
/* enable jumbo frame support at MAC level */ | /* enable jumbo frame support at MAC level */ | ||||
status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); | status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); | ||||
if (status) | if (status) | ||||
goto err_unroll_fltr_mgmt_struct; | goto err_unroll_fltr_mgmt_struct; | ||||
status = ice_init_hw_tbls(hw); | status = ice_init_hw_tbls(hw); | ||||
if (status) | if (status) | ||||
goto err_unroll_fltr_mgmt_struct; | goto err_unroll_fltr_mgmt_struct; | ||||
ice_init_lock(&hw->tnl_lock); | ice_init_lock(&hw->tnl_lock); | ||||
ice_init_vlan_mode_ops(hw); | |||||
return ICE_SUCCESS; | return ICE_SUCCESS; | ||||
err_unroll_fltr_mgmt_struct: | err_unroll_fltr_mgmt_struct: | ||||
ice_cleanup_fltr_mgmt_struct(hw); | ice_cleanup_fltr_mgmt_struct(hw); | ||||
err_unroll_sched: | err_unroll_sched: | ||||
ice_sched_cleanup_all(hw); | ice_sched_cleanup_all(hw); | ||||
err_unroll_alloc: | err_unroll_alloc: | ||||
ice_free(hw, hw->port_info); | ice_free(hw, hw->port_info); | ||||
▲ Show 20 Lines • Show All 835 Lines • ▼ Show 20 Lines | ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries, | ||||
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); | ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__); | ||||
cmd = &desc.params.sw_res_ctrl; | cmd = &desc.params.sw_res_ctrl; | ||||
if (!buf) | if (!buf) | ||||
return ICE_ERR_PARAM; | return ICE_ERR_PARAM; | ||||
if (buf_size < (num_entries * sizeof(buf->elem[0]))) | if (buf_size < FLEX_ARRAY_SIZE(buf, elem, num_entries)) | ||||
return ICE_ERR_PARAM; | return ICE_ERR_PARAM; | ||||
ice_fill_dflt_direct_cmd_desc(&desc, opc); | ice_fill_dflt_direct_cmd_desc(&desc, opc); | ||||
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); | desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); | ||||
cmd->num_entries = CPU_TO_LE16(num_entries); | cmd->num_entries = CPU_TO_LE16(num_entries); | ||||
▲ Show 20 Lines • Show All 264 Lines • ▼ Show 20 Lines | case ICE_AQC_CAPS_MSIX: | ||||
ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, | ice_debug(hw, ICE_DBG_INIT, "%s: num_msix_vectors = %d\n", prefix, | ||||
caps->num_msix_vectors); | caps->num_msix_vectors); | ||||
ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, | ice_debug(hw, ICE_DBG_INIT, "%s: msix_vector_first_id = %d\n", prefix, | ||||
caps->msix_vector_first_id); | caps->msix_vector_first_id); | ||||
break; | break; | ||||
case ICE_AQC_CAPS_NVM_VER: | case ICE_AQC_CAPS_NVM_VER: | ||||
break; | break; | ||||
case ICE_AQC_CAPS_NVM_MGMT: | case ICE_AQC_CAPS_NVM_MGMT: | ||||
caps->sec_rev_disabled = | |||||
(number & ICE_NVM_MGMT_SEC_REV_DISABLED) ? | |||||
true : false; | |||||
ice_debug(hw, ICE_DBG_INIT, "%s: sec_rev_disabled = %d\n", prefix, | |||||
caps->sec_rev_disabled); | |||||
caps->update_disabled = | |||||
(number & ICE_NVM_MGMT_UPDATE_DISABLED) ? | |||||
true : false; | |||||
ice_debug(hw, ICE_DBG_INIT, "%s: update_disabled = %d\n", prefix, | |||||
caps->update_disabled); | |||||
caps->nvm_unified_update = | caps->nvm_unified_update = | ||||
(number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? | (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ? | ||||
true : false; | true : false; | ||||
ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, | ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix, | ||||
caps->nvm_unified_update); | caps->nvm_unified_update); | ||||
break; | break; | ||||
case ICE_AQC_CAPS_CEM: | case ICE_AQC_CAPS_CEM: | ||||
caps->mgmt_cem = (number == 1); | caps->mgmt_cem = (number == 1); | ||||
▲ Show 20 Lines • Show All 391 Lines • ▼ Show 20 Lines | |||||
/** | /** | ||||
* ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode | * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
*/ | */ | ||||
void ice_set_safe_mode_caps(struct ice_hw *hw) | void ice_set_safe_mode_caps(struct ice_hw *hw) | ||||
{ | { | ||||
struct ice_hw_func_caps *func_caps = &hw->func_caps; | struct ice_hw_func_caps *func_caps = &hw->func_caps; | ||||
struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; | struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; | ||||
u32 valid_func, rxq_first_id, txq_first_id; | struct ice_hw_common_caps cached_caps; | ||||
u32 msix_vector_first_id, max_mtu; | |||||
u32 num_funcs; | u32 num_funcs; | ||||
/* cache some func_caps values that should be restored after memset */ | /* cache some func_caps values that should be restored after memset */ | ||||
valid_func = func_caps->common_cap.valid_functions; | cached_caps = func_caps->common_cap; | ||||
txq_first_id = func_caps->common_cap.txq_first_id; | |||||
rxq_first_id = func_caps->common_cap.rxq_first_id; | |||||
msix_vector_first_id = func_caps->common_cap.msix_vector_first_id; | |||||
max_mtu = func_caps->common_cap.max_mtu; | |||||
/* unset func capabilities */ | /* unset func capabilities */ | ||||
memset(func_caps, 0, sizeof(*func_caps)); | memset(func_caps, 0, sizeof(*func_caps)); | ||||
#define ICE_RESTORE_FUNC_CAP(name) \ | |||||
func_caps->common_cap.name = cached_caps.name | |||||
/* restore cached values */ | /* restore cached values */ | ||||
func_caps->common_cap.valid_functions = valid_func; | ICE_RESTORE_FUNC_CAP(valid_functions); | ||||
func_caps->common_cap.txq_first_id = txq_first_id; | ICE_RESTORE_FUNC_CAP(txq_first_id); | ||||
func_caps->common_cap.rxq_first_id = rxq_first_id; | ICE_RESTORE_FUNC_CAP(rxq_first_id); | ||||
func_caps->common_cap.msix_vector_first_id = msix_vector_first_id; | ICE_RESTORE_FUNC_CAP(msix_vector_first_id); | ||||
func_caps->common_cap.max_mtu = max_mtu; | ICE_RESTORE_FUNC_CAP(max_mtu); | ||||
ICE_RESTORE_FUNC_CAP(nvm_unified_update); | |||||
/* one Tx and one Rx queue in safe mode */ | /* one Tx and one Rx queue in safe mode */ | ||||
func_caps->common_cap.num_rxq = 1; | func_caps->common_cap.num_rxq = 1; | ||||
func_caps->common_cap.num_txq = 1; | func_caps->common_cap.num_txq = 1; | ||||
/* two MSIX vectors, one for traffic and one for misc causes */ | /* two MSIX vectors, one for traffic and one for misc causes */ | ||||
func_caps->common_cap.num_msix_vectors = 2; | func_caps->common_cap.num_msix_vectors = 2; | ||||
func_caps->guar_num_vsi = 1; | func_caps->guar_num_vsi = 1; | ||||
/* cache some dev_caps values that should be restored after memset */ | /* cache some dev_caps values that should be restored after memset */ | ||||
valid_func = dev_caps->common_cap.valid_functions; | cached_caps = dev_caps->common_cap; | ||||
txq_first_id = dev_caps->common_cap.txq_first_id; | |||||
rxq_first_id = dev_caps->common_cap.rxq_first_id; | |||||
msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id; | |||||
max_mtu = dev_caps->common_cap.max_mtu; | |||||
num_funcs = dev_caps->num_funcs; | num_funcs = dev_caps->num_funcs; | ||||
/* unset dev capabilities */ | /* unset dev capabilities */ | ||||
memset(dev_caps, 0, sizeof(*dev_caps)); | memset(dev_caps, 0, sizeof(*dev_caps)); | ||||
#define ICE_RESTORE_DEV_CAP(name) \ | |||||
dev_caps->common_cap.name = cached_caps.name | |||||
/* restore cached values */ | /* restore cached values */ | ||||
dev_caps->common_cap.valid_functions = valid_func; | ICE_RESTORE_DEV_CAP(valid_functions); | ||||
dev_caps->common_cap.txq_first_id = txq_first_id; | ICE_RESTORE_DEV_CAP(txq_first_id); | ||||
dev_caps->common_cap.rxq_first_id = rxq_first_id; | ICE_RESTORE_DEV_CAP(rxq_first_id); | ||||
dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id; | ICE_RESTORE_DEV_CAP(msix_vector_first_id); | ||||
dev_caps->common_cap.max_mtu = max_mtu; | ICE_RESTORE_DEV_CAP(max_mtu); | ||||
ICE_RESTORE_DEV_CAP(nvm_unified_update); | |||||
dev_caps->num_funcs = num_funcs; | dev_caps->num_funcs = num_funcs; | ||||
/* one Tx and one Rx queue per function in safe mode */ | /* one Tx and one Rx queue per function in safe mode */ | ||||
dev_caps->common_cap.num_rxq = num_funcs; | dev_caps->common_cap.num_rxq = num_funcs; | ||||
dev_caps->common_cap.num_txq = num_funcs; | dev_caps->common_cap.num_txq = num_funcs; | ||||
/* two MSIX vectors per function */ | /* two MSIX vectors per function */ | ||||
dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; | dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; | ||||
Show All 29 Lines | |||||
{ | { | ||||
struct ice_aqc_manage_mac_write *cmd; | struct ice_aqc_manage_mac_write *cmd; | ||||
struct ice_aq_desc desc; | struct ice_aq_desc desc; | ||||
cmd = &desc.params.mac_write; | cmd = &desc.params.mac_write; | ||||
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write); | ||||
cmd->flags = flags; | cmd->flags = flags; | ||||
ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_DMA); | ice_memcpy(cmd->mac_addr, mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA); | ||||
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); | ||||
} | } | ||||
/** | /** | ||||
* ice_aq_clear_pxe_mode | * ice_aq_clear_pxe_mode | ||||
* @hw: pointer to the HW struct | * @hw: pointer to the HW struct | ||||
* | * | ||||
▲ Show 20 Lines • Show All 319 Lines • ▼ Show 20 Lines | if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { | ||||
pcaps = (struct ice_aqc_get_phy_caps_data *) | pcaps = (struct ice_aqc_get_phy_caps_data *) | ||||
ice_malloc(hw, sizeof(*pcaps)); | ice_malloc(hw, sizeof(*pcaps)); | ||||
if (!pcaps) | if (!pcaps) | ||||
return ICE_ERR_NO_MEMORY; | return ICE_ERR_NO_MEMORY; | ||||
status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, | status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP, | ||||
pcaps, NULL); | pcaps, NULL); | ||||
if (status == ICE_SUCCESS) | |||||
ice_memcpy(li->module_type, &pcaps->module_type, | |||||
sizeof(li->module_type), | |||||
ICE_NONDMA_TO_NONDMA); | |||||
ice_free(hw, pcaps); | ice_free(hw, pcaps); | ||||
} | } | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* ice_cache_phy_user_req | * ice_cache_phy_user_req | ||||
▲ Show 20 Lines • Show All 547 Lines • ▼ Show 20 Lines | ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr, | ||||
struct ice_aq_desc desc; | struct ice_aq_desc desc; | ||||
enum ice_status status; | enum ice_status status; | ||||
if (!data || (mem_addr & 0xff00)) | if (!data || (mem_addr & 0xff00)) | ||||
return ICE_ERR_PARAM; | return ICE_ERR_PARAM; | ||||
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom); | ||||
cmd = &desc.params.read_write_sff_param; | cmd = &desc.params.read_write_sff_param; | ||||
desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF); | desc.flags = CPU_TO_LE16(ICE_AQ_FLAG_RD); | ||||
cmd->lport_num = (u8)(lport & 0xff); | cmd->lport_num = (u8)(lport & 0xff); | ||||
cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); | cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); | ||||
cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & | cmd->i2c_bus_addr = CPU_TO_LE16(((bus_addr >> 1) & | ||||
ICE_AQC_SFF_I2CBUS_7BIT_M) | | ICE_AQC_SFF_I2CBUS_7BIT_M) | | ||||
((set_page << | ((set_page << | ||||
ICE_AQC_SFF_SET_EEPROM_PAGE_S) & | ICE_AQC_SFF_SET_EEPROM_PAGE_S) & | ||||
ICE_AQC_SFF_SET_EEPROM_PAGE_M)); | ICE_AQC_SFF_SET_EEPROM_PAGE_M)); | ||||
cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); | cmd->i2c_mem_addr = CPU_TO_LE16(mem_addr & 0xff); | ||||
cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); | cmd->eeprom_page = CPU_TO_LE16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S); | ||||
if (write) | if (write) | ||||
cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); | cmd->i2c_bus_addr |= CPU_TO_LE16(ICE_AQC_SFF_IS_WRITE); | ||||
status = ice_aq_send_cmd(hw, &desc, data, length, cd); | status = ice_aq_send_cmd(hw, &desc, data, length, cd); | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* __ice_aq_get_set_rss_lut | * __ice_aq_get_set_rss_lut | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @vsi_id: VSI FW index | * @params: RSS LUT parameters | ||||
* @lut_type: LUT table type | |||||
* @lut: pointer to the LUT buffer provided by the caller | |||||
* @lut_size: size of the LUT buffer | |||||
* @glob_lut_idx: global LUT index | |||||
* @set: set true to set the table, false to get the table | * @set: set true to set the table, false to get the table | ||||
* | * | ||||
* Internal function to get (0x0B05) or set (0x0B03) RSS look up table | * Internal function to get (0x0B05) or set (0x0B03) RSS look up table | ||||
*/ | */ | ||||
static enum ice_status | static enum ice_status | ||||
__ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut, | __ice_aq_get_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *params, bool set) | ||||
u16 lut_size, u8 glob_lut_idx, bool set) | |||||
{ | { | ||||
u16 flags = 0, vsi_id, lut_type, lut_size, glob_lut_idx, vsi_handle; | |||||
struct ice_aqc_get_set_rss_lut *cmd_resp; | struct ice_aqc_get_set_rss_lut *cmd_resp; | ||||
struct ice_aq_desc desc; | struct ice_aq_desc desc; | ||||
enum ice_status status; | enum ice_status status; | ||||
u16 flags = 0; | u8 *lut; | ||||
if (!params) | |||||
return ICE_ERR_PARAM; | |||||
vsi_handle = params->vsi_handle; | |||||
lut = params->lut; | |||||
if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) | |||||
return ICE_ERR_PARAM; | |||||
lut_size = params->lut_size; | |||||
lut_type = params->lut_type; | |||||
glob_lut_idx = params->global_lut_id; | |||||
vsi_id = ice_get_hw_vsi_num(hw, vsi_handle); | |||||
cmd_resp = &desc.params.get_set_rss_lut; | cmd_resp = &desc.params.get_set_rss_lut; | ||||
if (set) { | if (set) { | ||||
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut); | ||||
desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); | desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD); | ||||
} else { | } else { | ||||
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); | ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut); | ||||
} | } | ||||
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines | |||||
ice_aq_get_set_rss_lut_exit: | ice_aq_get_set_rss_lut_exit: | ||||
return status; | return status; | ||||
} | } | ||||
/** | /** | ||||
* ice_aq_get_rss_lut | * ice_aq_get_rss_lut | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @vsi_handle: software VSI handle | * @get_params: RSS LUT parameters used to specify which RSS LUT to get | ||||
* @lut_type: LUT table type | |||||
* @lut: pointer to the LUT buffer provided by the caller | |||||
* @lut_size: size of the LUT buffer | |||||
* | * | ||||
* get the RSS lookup table, PF or VSI type | * get the RSS lookup table, PF or VSI type | ||||
*/ | */ | ||||
enum ice_status | enum ice_status | ||||
ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, | ice_aq_get_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *get_params) | ||||
u8 *lut, u16 lut_size) | |||||
{ | { | ||||
if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) | return __ice_aq_get_set_rss_lut(hw, get_params, false); | ||||
return ICE_ERR_PARAM; | |||||
return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), | |||||
lut_type, lut, lut_size, 0, false); | |||||
} | } | ||||
/** | /** | ||||
* ice_aq_set_rss_lut | * ice_aq_set_rss_lut | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* @vsi_handle: software VSI handle | * @set_params: RSS LUT parameters used to specify how to set the RSS LUT | ||||
* @lut_type: LUT table type | |||||
* @lut: pointer to the LUT buffer provided by the caller | |||||
* @lut_size: size of the LUT buffer | |||||
* | * | ||||
* set the RSS lookup table, PF or VSI type | * set the RSS lookup table, PF or VSI type | ||||
*/ | */ | ||||
enum ice_status | enum ice_status | ||||
ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, | ice_aq_set_rss_lut(struct ice_hw *hw, struct ice_aq_get_set_rss_lut_params *set_params) | ||||
u8 *lut, u16 lut_size) | |||||
{ | { | ||||
if (!ice_is_vsi_valid(hw, vsi_handle) || !lut) | return __ice_aq_get_set_rss_lut(hw, set_params, true); | ||||
return ICE_ERR_PARAM; | |||||
return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle), | |||||
lut_type, lut, lut_size, 0, true); | |||||
} | } | ||||
/** | /** | ||||
* __ice_aq_get_set_rss_key | * __ice_aq_get_set_rss_key | ||||
* @hw: pointer to the HW struct | * @hw: pointer to the HW struct | ||||
* @vsi_id: VSI FW index | * @vsi_id: VSI FW index | ||||
* @key: pointer to key info struct | * @key: pointer to key info struct | ||||
* @set: set true to set the key, false to get the key | * @set: set true to set the key, false to get the key | ||||
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