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	lower_sharedpage_init = 1;			lower_sharedpage_init = 1;
	if (CPUID_TO_FAMILY(cpu_id) == 0x17 \|\|			if (CPUID_TO_FAMILY(cpu_id) == 0x17 \|\|
	CPUID_TO_FAMILY(cpu_id) == 0x18) {			CPUID_TO_FAMILY(cpu_id) == 0x18) {
	hw_lower_amd64_sharedpage = 1;			hw_lower_amd64_sharedpage = 1;
	}			}
	}			}
	}			}

				void init_amd_sem(void* dummy)
				{
				uint64_t msr;

				/* FIXME: should prob check how much mem is in the current system. */
				if (amd_encrypted_memory & AMD_SEM_SUPPORTED) {
				/* pte bit to be or'd to use ecnryption */
				// FIXME: every core writes this field at the same time?!
				pg_sem_c = 1 << (amd_encrypted_memory2 & AMD_SEM_CBIT_MASK);
				jo_bruelltuete.comAuthorUnsubmitted Done Inline Actions ugh... i wasted a lot of time chasing down a bug here. this bit shift, as written, is 32 bit. but it needs to be 64 bits. a bit embarrassing tbh... jo_bruelltuete.com: ugh... i wasted a lot of time chasing down a bug here. this bit shift, as written, is 32 bit.

				/* enable the c bit for ptes. */
				msr = rdmsr(MSR_SYSCFG);
				msr \|= 1 << 23;
				wrmsr(MSR_SYSCFG, msr);
				}
				}

	/*			/*
	* Initialize special VIA features			* Initialize special VIA features
	*/			*/
	static void			static void
	init_via(void)			init_via(void)
	{			{
	u_int regs[4], val;			u_int regs[4], val;

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