Differential D27889 Diff 83333 sys/arm/ti/clk/ti_gate_clock.c

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sys/arm/ti/clk/ti_gate_clock.c

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	#include <sys/kernel.h>			#include <sys/kernel.h>
	#include <sys/module.h>			#include <sys/module.h>
	#include <sys/systm.h>			#include <sys/systm.h>
	#include <sys/libkern.h>			#include <sys/libkern.h>

	#include <machine/bus.h>			#include <machine/bus.h>
	#include <dev/fdt/simplebus.h>			#include <dev/fdt/simplebus.h>

	#include <dev/extres/clk/clk_gate.h>
	#include <dev/ofw/ofw_bus.h>			#include <dev/ofw/ofw_bus.h>
	#include <dev/ofw/ofw_bus_subr.h>			#include <dev/ofw/ofw_bus_subr.h>
				#include <dev/extres/clk/clk_gate.h>
				#include <dev/extres/syscon/syscon.h>

	#include "clock_common.h"			#include "clock_common.h"
				#include "clkdev_if.h"
				#include "syscon_if.h"

	#define DEBUG_GATE 0			#define DEBUG_GATE 0

	#if DEBUG_GATE			#if DEBUG_GATE
	#define DPRINTF(dev, msg...) device_printf(dev, msg)			#define DPRINTF(dev, msg...) device_printf(dev, msg)
	#else			#else
	#define DPRINTF(dev, msg...)			#define DPRINTF(dev, msg...)
	#endif			#endif

	/*			/*
	* Devicetree description			* Devicetree description
	* Documentation/devicetree/bindings/clock/ti/gate.txt			* Documentation/devicetree/bindings/clock/ti/gate.txt
	*/			*/

	struct ti_gate_softc {			struct ti_gate_softc {
	device_t sc_dev;			device_t dev;
	bool attach_done;
	uint8_t sc_type;			uint8_t sc_type;

	struct clk_gate_def gate_def;			struct clk_gate_def gate_def;
	struct clock_cell_info clock_cell;
	struct clkdom *clkdom;			struct clkdom *clkdom;
				struct syscon *syscon;
	};			};

	static int ti_gate_probe(device_t dev);			static int ti_gate_probe(device_t dev);
	static int ti_gate_attach(device_t dev);			static int ti_gate_attach(device_t dev);
	static int ti_gate_detach(device_t dev);			static int ti_gate_detach(device_t dev);

	#define TI_GATE_CLOCK 7			#define TI_GATE_CLOCK 7
	#define TI_WAIT_GATE_CLOCK 6			#define TI_WAIT_GATE_CLOCK 6
	#define TI_DSS_GATE_CLOCK 5			#define TI_DSS_GATE_CLOCK 5
	#define TI_AM35XX_GATE_CLOCK 4			#define TI_AM35XX_GATE_CLOCK 4
	#define TI_CLKDM_GATE_CLOCK 3			#define TI_CLKDM_GATE_CLOCK 3
	#define TI_HSDIV_GATE_CLOCK 2			#define TI_HSDIV_GATE_CLOCK 2
	#define TI_COMPOSITE_NO_WAIT_GATE_CLOCK 1			#define TI_COMPOSITE_NO_WAIT_GATE_CLOCK 1
	#define TI_GATE_END 0			#define TI_GATE_END 0

	static struct ofw_compat_data compat_data[] = {			static struct ofw_compat_data compat_data[] = {
	{ "ti,gate-clock", TI_GATE_CLOCK },			{ "ti,gate-clock", TI_GATE_CLOCK },
	{ "ti,wait-gate-clock", TI_WAIT_GATE_CLOCK },			{ "ti,wait-gate-clock", TI_WAIT_GATE_CLOCK },
	{ "ti,dss-gate-clock", TI_DSS_GATE_CLOCK },			{ "ti,dss-gate-clock", TI_DSS_GATE_CLOCK },
	{ "ti,am35xx-gate-clock", TI_AM35XX_GATE_CLOCK },			{ "ti,am35xx-gate-clock", TI_AM35XX_GATE_CLOCK },
	{ "ti,clkdm-gate-clock", TI_CLKDM_GATE_CLOCK },			/* For now, dont support clkdm-gate-clock */
				/* { "ti,clkdm-gate-clock", TI_CLKDM_GATE_CLOCK }, */
	{ "ti,hsdiv-gate-cloc", TI_HSDIV_GATE_CLOCK },			{ "ti,hsdiv-gate-cloc", TI_HSDIV_GATE_CLOCK },
	{ "ti,composite-no-wait-gate-clock", TI_COMPOSITE_NO_WAIT_GATE_CLOCK },			{ "ti,composite-no-wait-gate-clock", TI_COMPOSITE_NO_WAIT_GATE_CLOCK },
	{ NULL, TI_GATE_END }			{ NULL, TI_GATE_END }
	};			};

				PLIST(ehrpwm0_tbclk_parent) = { "l4ls_gclk" };
				PLIST(ehrpwm1_tbclk_parent) = { "l4ls_gclk" };
				PLIST(ehrpwm2_tbclk_parent) = { "l4ls_gclk" };
				PLIST(mmu_fck_parent) = { "dpll_core_m4_ck@480" };
				PLIST(usbotg_fck_parent) = { "dpll_per_ck@48c" };
				PLIST(ieee5000_fck_parent) = { "dpll_core_m4_div2_ck" };
				PLIST(clkout2_ck_parent) = { "clkout2_div_ck@700" };


				static struct parent_lookup_table gate_parent_table[] = {
				{
				"ehrpwm0_tbclk@44e10664",
				nitems(ehrpwm0_tbclk_parent),
				ehrpwm0_tbclk_parent
				},
				{
				"ehrpwm1_tbclk@44e10664",
				nitems(ehrpwm1_tbclk_parent),
				ehrpwm1_tbclk_parent
				},
				{
				"ehrpwm2_tbclk@44e10664",
				nitems(ehrpwm2_tbclk_parent),
				ehrpwm2_tbclk_parent
				},
				{
				"mmu_fck@914",
				nitems(mmu_fck_parent),
				mmu_fck_parent
				},
				{
				"usbotg_fck@47c",
				nitems(usbotg_fck_parent),
				usbotg_fck_parent
				},
				{
				"ieee5000_fck@e4",
				nitems(ieee5000_fck_parent),
				ieee5000_fck_parent
				},
				{
				"clkout2_ck@700",
				nitems(clkout2_ck_parent),
				clkout2_ck_parent
				},
				};


	static int			static int
	ti_gate_probe(device_t dev)			ti_gate_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val)
	{			{
	if (!ofw_bus_status_okay(dev))			struct ti_gate_softc *sc;
	return (ENXIO);

	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)			sc = device_get_softc(dev);
	return (ENXIO);			DPRINTF(sc->dev, "gate_clkdev_write_4: addr %x val %x\n",
				addr, val);
				return (SYSCON_UNLOCKED_WRITE_4(sc->syscon, addr, val));
				}

	device_set_desc(dev, "TI Gate Clock");			static int
				ti_gate_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
				{
				struct ti_gate_softc *sc;

	return (BUS_PROBE_DEFAULT);			sc = device_get_softc(dev);

				*val = SYSCON_UNLOCKED_READ_4(sc->syscon, addr);
				DPRINTF(sc->dev, "gate_clkdev_write_4: addr %x val %x\n",
				addr, *val);
				return (0);
	}			}

	static int			static int
	register_clk(struct ti_gate_softc *sc) {			ti_gate_clkdev_modify_4(device_t dev, bus_addr_t addr,
	int err;			uint32_t clear_mask, uint32_t set_mask)
	sc->clkdom = clkdom_create(sc->sc_dev);			{
	if (sc->clkdom == NULL) {			struct ti_gate_softc *sc;
	DPRINTF(sc->sc_dev, "Failed to create clkdom\n");
	return ENXIO;			sc = device_get_softc(dev);
				DPRINTF(sc->dev, "clkdev_modify_4: addr %x clear_mask %x set_mask %x\n",
				addr, clear_mask, set_mask);
				return (SYSCON_UNLOCKED_MODIFY_4(sc->syscon, addr, clear_mask,
				set_mask));
	}			}

	err = clknode_gate_register(sc->clkdom, &sc->gate_def);			static void
	if (err) {			ti_gate_clkdev_device_lock(device_t dev)
	DPRINTF(sc->sc_dev, "clknode_gate_register failed %x\n", err);			{
	return ENXIO;			struct ti_gate_softc *sc;

				sc = device_get_softc(dev);
				DPRINTF(sc->dev, "ti_gate_clkdev_device_lock\n");
				SYSCON_DEVICE_LOCK(sc->syscon->pdev);
	}			}

	err = clkdom_finit(sc->clkdom);			static void
	if (err) {			ti_gate_clkdev_device_unlock(device_t dev)
	DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err);			{
	return ENXIO;			struct ti_gate_softc *sc;

				sc = device_get_softc(dev);
				DPRINTF(sc->dev, "ti_gate_clkdev_device_unlock\n");
				SYSCON_DEVICE_UNLOCK(sc->syscon->pdev);
	}			}

	return (0);			static int
				ti_gate_probe(device_t dev)
				{
				if (!ofw_bus_status_okay(dev))
				return (ENXIO);

				if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
				return (ENXIO);

				device_set_desc(dev, "TI Gate Clock");

				return (BUS_PROBE_DEFAULT);
	}			}

	static int			static int
	ti_gate_attach(device_t dev)			ti_gate_attach(device_t dev)
	{			{
	struct ti_gate_softc *sc;			struct ti_gate_softc *sc;
	phandle_t node;			phandle_t node;
	int err;			int err, index;
	cell_t value;			cell_t value;
				const char *node_name;

	sc = device_get_softc(dev);			sc = device_get_softc(dev);
	sc->sc_dev = dev;			sc->dev = dev;
	node = ofw_bus_get_node(dev);			node = ofw_bus_get_node(dev);

				/* Get syscon */
				err = SYSCON_GET_HANDLE(dev, &sc->syscon);
				if (err != 0) {
				panic("Cannot get syscon handle.\n");
				}

				node_name = ofw_bus_get_name(dev);
				if (node_name == NULL) {
				panic("Cannot get name of the clock node");
				}

	/* Get the compatible type */			/* Get the compatible type */
	sc->sc_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;			sc->sc_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;

	/* Get the content of reg properties */			/* Get the content of reg properties */
	if (sc->sc_type != TI_CLKDM_GATE_CLOCK) {			if (!OF_hasprop(node, "reg")) {
				oskar.holmlund_ohdata.seAuthorUnsubmitted Done Inline Actions For the am335x this is actually not needed to handle the ti,clkdm-gate-clock, its used on some omap3 and omap44 devices. reg : offset for register controlling adjustable gate, not needed for ti,clkdm-gate-clock type https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/ti/gate.txt oskar.holmlund_ohdata.se: For the am335x this is actually not needed to handle the ti,clkdm-gate-clock, its used on some…
				device_printf(sc->dev, "missing reg property\n");
				return (ENXIO);
				}
	OF_getencprop(node, "reg", &value, sizeof(value));			OF_getencprop(node, "reg", &value, sizeof(value));
	sc->gate_def.offset = value;			sc->gate_def.offset = value;
	}
	#if DEBUG_GATE
	else {
	DPRINTF(sc->sc_dev, "no reg (TI_CLKDM_GATE_CLOCK)\n");
	}
	#endif

	if (OF_hasprop(node, "ti,bit-shift")) {			if (OF_hasprop(node, "ti,bit-shift")) {
	OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));			OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));
	sc->gate_def.shift = value;			sc->gate_def.shift = value;
	DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->gate_def.shift);			DPRINTF(sc->dev, "ti,bit-shift => shift %x\n",
				sc->gate_def.shift);
	}			}
	if (OF_hasprop(node, "ti,set-bit-to-disable")) {			if (OF_hasprop(node, "ti,set-bit-to-disable")) {
	sc->gate_def.on_value = 0;			sc->gate_def.on_value = 0;
	sc->gate_def.off_value = 1;			sc->gate_def.off_value = 1;
	DPRINTF(sc->sc_dev,			DPRINTF(sc->dev,
	"on_value = 0, off_value = 1 (ti,set-bit-to-disable)\n");			"ti,set-bit-to-disable (on = 0, off = 1)\n");
	} else {			} else {
	sc->gate_def.on_value = 1;			sc->gate_def.on_value = 1;
	sc->gate_def.off_value = 0;			sc->gate_def.off_value = 0;
	DPRINTF(sc->sc_dev, "on_value = 1, off_value = 0\n");			DPRINTF(sc->dev,
				"!ti,set-bit-to-disable (on = 1, off = 0)\n");
	}			}

	sc->gate_def.gate_flags = 0x0;			sc->gate_def.gate_flags = 0x0;

	read_clock_cells(sc->sc_dev, &sc->clock_cell);

	create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef);			/* Find parent in lookup table */
				for (index = 0; index < nitems(gate_parent_table); index++) {
				if (strcmp(node_name, gate_parent_table[index].node_name) == 0)
				break;
				}

	/* Calculate mask */			if (index == nitems(gate_parent_table))
	sc->gate_def.mask = (1 << fls(sc->clock_cell.num_real_clocks)) - 1;			panic("Cant find clock %s\n", node_name);
	DPRINTF(sc->sc_dev, "num_real_clocks %x gate_def.mask %x\n",
	sc->clock_cell.num_real_clocks, sc->gate_def.mask);

	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef);			DPRINTF(dev, "%s at gate_parent_table[%d]\n",
				node_name, index);

	if (err) {			/* Fill clknode_init_def */
	/* free_clkdef will be called in ti_gate_new_pass */			sc->gate_def.clkdef.id = 1;
	DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");			sc->gate_def.clkdef.flags = CLK_NODE_STATIC_STRINGS;
	return (bus_generic_attach(sc->sc_dev));			sc->gate_def.clkdef.name = gate_parent_table[index].node_name;
	}			sc->gate_def.clkdef.parent_cnt = gate_parent_table[index].parent_cnt;
				sc->gate_def.clkdef.parent_names =gate_parent_table[index].parent_names;

	err = register_clk(sc);			/* Calculate mask */
				sc->gate_def.mask = (1 << fls(sc->gate_def.clkdef.parent_cnt)) - 1;
				DPRINTF(sc->dev, "num_real_clocks %x gate_def.mask %x\n",
				sc->gate_def.clkdef.parent_cnt,
				sc->gate_def.mask);

	if (err) {			sc->clkdom = clkdom_create(sc->dev);
	/* free_clkdef will be called in ti_gate_new_pass */			if (sc->clkdom == NULL) {
	DPRINTF(sc->sc_dev, "register_clk failed\n");			DPRINTF(sc->dev, "Failed to create clkdom\n");
	return (bus_generic_attach(sc->sc_dev));			return ENXIO;
	}			}

	sc->attach_done = true;			err = clknode_gate_register(sc->clkdom, &sc->gate_def);
				if (err != 0) {
				DPRINTF(sc->dev, "clknode_gate_register failed %x\n", err);
				return ENXIO;
				}

	free_clkdef(&sc->gate_def.clkdef);			err = clkdom_finit(sc->clkdom);
				if (err != 0) {
				DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err);
				return ENXIO;
				}

	return (bus_generic_attach(sc->sc_dev));			return (bus_generic_attach(sc->dev));
	}			}

	static int			static int
	ti_gate_detach(device_t dev)			ti_gate_detach(device_t dev)
	{			{
	return (EBUSY);			return (EBUSY);
	}			}

	static void
	ti_gate_new_pass(device_t dev) {
	struct ti_gate_softc *sc;
	int err;

	sc = device_get_softc(dev);

	if (sc->attach_done) {
	return;
	}

	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef);
	if (err) {
	/* free_clkdef will be called in later call to ti_gate_new_pass */
	DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n");
	return;
	}

	err = register_clk(sc);
	if (err) {
	/* free_clkdef will be called in later call to ti_gate_new_pass */
	DPRINTF(sc->sc_dev, "new_pass register_clk failed\n");
	return;
	}

	sc->attach_done = true;

	free_clkdef(&sc->gate_def.clkdef);
	}

	static device_method_t ti_gate_methods[] = {			static device_method_t ti_gate_methods[] = {
	/* Device interface */			/* Device interface */
	DEVMETHOD(device_probe, ti_gate_probe),			DEVMETHOD(device_probe, ti_gate_probe),
	DEVMETHOD(device_attach, ti_gate_attach),			DEVMETHOD(device_attach, ti_gate_attach),
	DEVMETHOD(device_detach, ti_gate_detach),			DEVMETHOD(device_detach, ti_gate_detach),

	/* Bus interface */			/* Clock device interface */
	DEVMETHOD(bus_new_pass, ti_gate_new_pass),			DEVMETHOD(clkdev_device_lock, ti_gate_clkdev_device_lock),
				DEVMETHOD(clkdev_device_unlock, ti_gate_clkdev_device_unlock),
				DEVMETHOD(clkdev_read_4, ti_gate_clkdev_read_4),
				DEVMETHOD(clkdev_write_4, ti_gate_clkdev_write_4),
				DEVMETHOD(clkdev_modify_4, ti_gate_clkdev_modify_4),

	DEVMETHOD_END			DEVMETHOD_END
	};			};

	DEFINE_CLASS_0(ti_gate, ti_gate_driver, ti_gate_methods,			DEFINE_CLASS_0(ti_gate, ti_gate_driver, ti_gate_methods,
	sizeof(struct ti_gate_softc));			sizeof(struct ti_gate_softc));

	static devclass_t ti_gate_devclass;			static devclass_t ti_gate_devclass;

	EARLY_DRIVER_MODULE(ti_gate, simplebus, ti_gate_driver,			EARLY_DRIVER_MODULE(ti_gate, simplebus, ti_gate_driver,
	ti_gate_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);			ti_gate_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
	MODULE_VERSION(ti_gate, 1);			MODULE_VERSION(ti_gate, 1);