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sys/arm/ti/clk/ti_dpll_clock.c
Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | |||||
* Devicetree description | * Devicetree description | ||||
* Documentation/devicetree/bindings/clock/ti/dpll.txt | * Documentation/devicetree/bindings/clock/ti/dpll.txt | ||||
*/ | */ | ||||
struct ti_dpll_softc { | struct ti_dpll_softc { | ||||
device_t dev; | device_t dev; | ||||
uint8_t dpll_type; | uint8_t dpll_type; | ||||
bool attach_done; | |||||
struct ti_clk_dpll_def dpll_def; | struct ti_clk_dpll_def dpll_def; | ||||
struct clock_cell_info clock_cell; | |||||
struct clkdom *clkdom; | struct clkdom *clkdom; | ||||
}; | }; | ||||
static int ti_dpll_probe(device_t dev); | static int ti_dpll_probe(device_t dev); | ||||
static int ti_dpll_attach(device_t dev); | static int ti_dpll_attach(device_t dev); | ||||
static int ti_dpll_detach(device_t dev); | static int ti_dpll_detach(device_t dev); | ||||
#define TI_OMAP3_DPLL_CLOCK 17 | #define TI_OMAP3_DPLL_CLOCK 17 | ||||
Show All 31 Lines | static struct ofw_compat_data compat_data[] = { | ||||
{ "ti,am3-dpll-no-gate-j-type-clock",TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK }, | { "ti,am3-dpll-no-gate-j-type-clock",TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK }, | ||||
{ "ti,am3-dpll-clock", TI_AM3_DPLL_CLOCK }, | { "ti,am3-dpll-clock", TI_AM3_DPLL_CLOCK }, | ||||
{ "ti,am3-dpll-core-clock", TI_AM3_DPLL_CORE_CLOCK }, | { "ti,am3-dpll-core-clock", TI_AM3_DPLL_CORE_CLOCK }, | ||||
{ "ti,am3-dpll-x2-clock", TI_AM3_DPLL_X2_CLOCK }, | { "ti,am3-dpll-x2-clock", TI_AM3_DPLL_X2_CLOCK }, | ||||
{ "ti,omap2-dpll-core-clock", TI_OMAP2_DPLL_CORE_CLOCK }, | { "ti,omap2-dpll-core-clock", TI_OMAP2_DPLL_CORE_CLOCK }, | ||||
{ NULL, TI_DPLL_END } | { NULL, TI_DPLL_END } | ||||
}; | }; | ||||
static int | |||||
register_clk(struct ti_dpll_softc *sc) { | |||||
int err; | |||||
sc->clkdom = clkdom_create(sc->dev); | PLIST(dpll_core_ck_parent) = { "sys_clkin_ck@40", "sys_clkin_ck@40" }; | ||||
if (sc->clkdom == NULL) { | PLIST(dpll_core_x2_parent) = { "dpll_core_ck@490" }; | ||||
DPRINTF(sc->dev, "Failed to create clkdom\n"); | |||||
return (ENXIO); | |||||
} | |||||
err = ti_clknode_dpll_register(sc->clkdom, &sc->dpll_def); | PLIST(dpll_mpu_ck_parent) = { "sys_clkin_ck@40", "sys_clkin_ck@40" }; | ||||
if (err) { | |||||
DPRINTF(sc->dev, | |||||
"ti_clknode_dpll_register failed %x\n", err); | |||||
return (ENXIO); | |||||
} | |||||
err = clkdom_finit(sc->clkdom); | PLIST(dpll_ddr_ck_parent) = { "sys_clkin_ck@40", "sys_clkin_ck@40" }; | ||||
if (err) { | PLIST(dpll_ddr_m2_div2_ck_parent) = { "dpll_ddr_m2_ck@4a0" }; | ||||
DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err); | |||||
return (ENXIO); | |||||
} | |||||
return (0); | PLIST(dpll_disp_ck_parent) = { "sys_clkin_ck@40", "sys_clkin_ck@40" }; | ||||
} | |||||
PLIST(dpll_per_ck_parent) = { "sys_clkin_ck@40", "sys_clkin_ck@40" }; | |||||
PLIST(dpll_per_m2_div4_wkupdm_ck_parent) = { "dpll_per_m2_ck@4ac" }; | |||||
PLIST(dpll_per_m2_div4_ck_parent) = { "dpll_per_m2_ck@4ac" }; | |||||
static struct parent_lookup_table dpll_parent_table[] = { | |||||
{ | |||||
"dpll_core_ck@490", | |||||
nitems(dpll_core_ck_parent), | |||||
dpll_core_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_core_x2_ck", | |||||
nitems(dpll_core_x2_parent), | |||||
dpll_core_x2_parent | |||||
}, | |||||
{ | |||||
"dpll_mpu_ck@488", | |||||
nitems(dpll_mpu_ck_parent), | |||||
dpll_mpu_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_ddr_ck@494", | |||||
nitems(dpll_ddr_ck_parent), | |||||
dpll_ddr_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_ddr_m2_div2_ck", | |||||
nitems(dpll_ddr_m2_div2_ck_parent), | |||||
dpll_ddr_m2_div2_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_disp_ck@498", | |||||
nitems(dpll_disp_ck_parent), | |||||
dpll_disp_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_per_ck@48c", | |||||
nitems(dpll_per_ck_parent), | |||||
dpll_per_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_per_m2_div4_wkupdm_ck", | |||||
nitems(dpll_per_m2_div4_wkupdm_ck_parent), | |||||
dpll_per_m2_div4_wkupdm_ck_parent | |||||
}, | |||||
{ | |||||
"dpll_per_m2_div4_ck", | |||||
nitems(dpll_per_m2_div4_ck_parent), | |||||
dpll_per_m2_div4_ck_parent | |||||
}, | |||||
}; | |||||
static int | static int | ||||
ti_dpll_probe(device_t dev) | ti_dpll_probe(device_t dev) | ||||
{ | { | ||||
if (!ofw_bus_status_okay(dev)) | if (!ofw_bus_status_okay(dev)) | ||||
return (ENXIO); | return (ENXIO); | ||||
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) | if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) | ||||
return (ENXIO); | return (ENXIO); | ||||
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines | DPRINTF(sc->dev, "clkmode %x idlest %x clksel %x autoidle %x\n", | ||||
sc->dpll_def.ti_clksel_offset, | sc->dpll_def.ti_clksel_offset, | ||||
sc->dpll_def.ti_autoidle_offset); | sc->dpll_def.ti_autoidle_offset); | ||||
return (0); | return (0); | ||||
} | } | ||||
static int | static int | ||||
ti_dpll_attach(device_t dev) | ti_dpll_attach(device_t dev) | ||||
{ | { | ||||
struct ti_dpll_softc *sc; | struct ti_dpll_softc *sc; | ||||
phandle_t node; | phandle_t node; | ||||
int err; | int err, index; | ||||
const char *node_name; | |||||
sc = device_get_softc(dev); | sc = device_get_softc(dev); | ||||
sc->dev = dev; | sc->dev = dev; | ||||
sc->dpll_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; | sc->dpll_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; | ||||
node = ofw_bus_get_node(dev); | node = ofw_bus_get_node(dev); | ||||
node_name = ofw_bus_get_name(dev); | |||||
if (node_name == NULL) { | |||||
panic("Cannot get name of the clock node"); | |||||
} | |||||
/* Grab the content of reg properties */ | /* Grab the content of reg properties */ | ||||
parse_dpll_reg(sc); | parse_dpll_reg(sc); | ||||
/* default flags (OMAP4&AM335x) not present in the dts at moment */ | /* default flags (OMAP4&AM335x) not present in the dts at moment */ | ||||
sc->dpll_def.ti_clkmode_flags = MN_BYPASS_MODE_FLAG | LOCK_MODE_FLAG; | sc->dpll_def.ti_clkmode_flags = MN_BYPASS_MODE_FLAG | LOCK_MODE_FLAG; | ||||
if (OF_hasprop(node, "ti,low-power-stop")) { | if (OF_hasprop(node, "ti,low-power-stop")) { | ||||
sc->dpll_def.ti_clkmode_flags |= LOW_POWER_STOP_MODE_FLAG; | sc->dpll_def.ti_clkmode_flags |= LOW_POWER_STOP_MODE_FLAG; | ||||
} | } | ||||
if (OF_hasprop(node, "ti,low-power-bypass")) { | if (OF_hasprop(node, "ti,low-power-bypass")) { | ||||
sc->dpll_def.ti_clkmode_flags |= IDLE_BYPASS_LOW_POWER_MODE_FLAG; | sc->dpll_def.ti_clkmode_flags |= IDLE_BYPASS_LOW_POWER_MODE_FLAG; | ||||
} | } | ||||
if (OF_hasprop(node, "ti,lock")) { | if (OF_hasprop(node, "ti,lock")) { | ||||
sc->dpll_def.ti_clkmode_flags |= LOCK_MODE_FLAG; | sc->dpll_def.ti_clkmode_flags |= LOCK_MODE_FLAG; | ||||
} | } | ||||
read_clock_cells(sc->dev, &sc->clock_cell); | /* Find parent in lookup table */ | ||||
for (index = 0; index < nitems(dpll_parent_table); index++) { | |||||
if (strcmp(node_name, dpll_parent_table[index].node_name) == 0) | |||||
break; | |||||
} | |||||
create_clkdef(sc->dev, &sc->clock_cell, &sc->dpll_def.clkdef); | if (index == nitems(dpll_parent_table)) | ||||
panic("Cant find clock %s\n", node_name); | |||||
err = find_parent_clock_names(sc->dev, &sc->clock_cell, | DPRINTF(sc->dev, "%s at dpll_parent_table[%d]\n", node_name, index); | ||||
&sc->dpll_def.clkdef); | |||||
if (err) { | /* Fill clknode_init_def */ | ||||
/* free_clkdef will be called in ti_dpll_new_pass */ | sc->dpll_def.clkdef.id = 1; | ||||
DPRINTF(sc->dev, "find_parent_clock_names failed\n"); | sc->dpll_def.clkdef.name = dpll_parent_table[index].node_name; | ||||
return (bus_generic_attach(sc->dev)); | sc->dpll_def.clkdef.parent_cnt = dpll_parent_table[index].parent_cnt; | ||||
sc->dpll_def.clkdef.parent_names = | |||||
dpll_parent_table[index].parent_names; | |||||
sc->dpll_def.clkdef.flags = CLK_NODE_STATIC_STRINGS; | |||||
sc->clkdom = clkdom_create(sc->dev); | |||||
if (sc->clkdom == NULL) { | |||||
DPRINTF(sc->dev, "Failed to create clkdom\n"); | |||||
return (ENXIO); | |||||
} | } | ||||
err = register_clk(sc); | err = ti_clknode_dpll_register(sc->clkdom, &sc->dpll_def); | ||||
if (err != 0) { | |||||
DPRINTF(sc->dev, | |||||
"ti_clknode_dpll_register failed %x\n", err); | |||||
return (ENXIO); | |||||
} | |||||
if (err) { | err = clkdom_finit(sc->clkdom); | ||||
/* free_clkdef will be called in ti_dpll_new_pass */ | if (err != 0) { | ||||
DPRINTF(sc->dev, "register_clk failed\n"); | DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err); | ||||
return (bus_generic_attach(sc->dev)); | return (ENXIO); | ||||
} | } | ||||
sc->attach_done = true; | |||||
free_clkdef(&sc->dpll_def.clkdef); | |||||
return (bus_generic_attach(sc->dev)); | return (bus_generic_attach(sc->dev)); | ||||
} | } | ||||
static int | static int | ||||
ti_dpll_detach(device_t dev) | ti_dpll_detach(device_t dev) | ||||
{ | { | ||||
return (EBUSY); | return (EBUSY); | ||||
} | } | ||||
static void | |||||
ti_dpll_new_pass(device_t dev) | |||||
{ | |||||
struct ti_dpll_softc *sc; | |||||
int err; | |||||
sc = device_get_softc(dev); | |||||
if (sc->attach_done) { | |||||
return; | |||||
} | |||||
err = find_parent_clock_names(sc->dev, &sc->clock_cell, | |||||
&sc->dpll_def.clkdef); | |||||
if (err) { | |||||
/* free_clkdef will be called in a later call to ti_dpll_new_pass */ | |||||
DPRINTF(sc->dev, | |||||
"new_pass find_parent_clock_names failed\n"); | |||||
return; | |||||
} | |||||
err = register_clk(sc); | |||||
if (err) { | |||||
/* free_clkdef will be called in a later call to ti_dpll_new_pass */ | |||||
DPRINTF(sc->dev, "new_pass register_clk failed\n"); | |||||
return; | |||||
} | |||||
sc->attach_done = true; | |||||
free_clkdef(&sc->dpll_def.clkdef); | |||||
} | |||||
static device_method_t ti_dpll_methods[] = { | static device_method_t ti_dpll_methods[] = { | ||||
/* Device interface */ | /* Device interface */ | ||||
DEVMETHOD(device_probe, ti_dpll_probe), | DEVMETHOD(device_probe, ti_dpll_probe), | ||||
DEVMETHOD(device_attach, ti_dpll_attach), | DEVMETHOD(device_attach, ti_dpll_attach), | ||||
DEVMETHOD(device_detach, ti_dpll_detach), | DEVMETHOD(device_detach, ti_dpll_detach), | ||||
/* Bus interface */ | |||||
DEVMETHOD(bus_new_pass, ti_dpll_new_pass), | |||||
DEVMETHOD_END | DEVMETHOD_END | ||||
}; | }; | ||||
DEFINE_CLASS_0(ti_dpll, ti_dpll_driver, ti_dpll_methods, | DEFINE_CLASS_0(ti_dpll, ti_dpll_driver, ti_dpll_methods, | ||||
sizeof(struct ti_dpll_softc)); | sizeof(struct ti_dpll_softc)); | ||||
static devclass_t ti_dpll_devclass; | static devclass_t ti_dpll_devclass; | ||||
EARLY_DRIVER_MODULE(ti_dpll, simplebus, ti_dpll_driver, | EARLY_DRIVER_MODULE(ti_dpll, simplebus, ti_dpll_driver, | ||||
ti_dpll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); | ti_dpll_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); | ||||
MODULE_VERSION(ti_dpll, 1); | MODULE_VERSION(ti_dpll, 1); |