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sys/arm/ti/clk/ti_clkctrl.c
Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines | |||||
#include <vm/vm_kern.h> | #include <vm/vm_kern.h> | ||||
#include <vm/pmap.h> | #include <vm/pmap.h> | ||||
#include <dev/fdt/simplebus.h> | #include <dev/fdt/simplebus.h> | ||||
#include <dev/ofw/ofw_bus.h> | #include <dev/ofw/ofw_bus.h> | ||||
#include <dev/ofw/ofw_bus_subr.h> | #include <dev/ofw/ofw_bus_subr.h> | ||||
#include <arm/ti/clk/clock_common.h> | |||||
#include <arm/ti/clk/ti_clk_clkctrl.h> | #include <arm/ti/clk/ti_clk_clkctrl.h> | ||||
#include <arm/ti/ti_omap4_cm.h> | #include <arm/ti/ti_omap4_cm.h> | ||||
#include <arm/ti/ti_cpuid.h> | #include <arm/ti/ti_cpuid.h> | ||||
#if 0 | #if 0 | ||||
#define DPRINTF(dev, msg...) device_printf(dev, msg) | #define DPRINTF(dev, msg...) device_printf(dev, msg) | ||||
#else | #else | ||||
#define DPRINTF(dev, msg...) | #define DPRINTF(dev, msg...) | ||||
Show All 22 Lines | |||||
}; | }; | ||||
struct ti_clkctrl_softc { | struct ti_clkctrl_softc { | ||||
device_t dev; | device_t dev; | ||||
struct clkdom *clkdom; | struct clkdom *clkdom; | ||||
}; | }; | ||||
/* reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; */ | |||||
/* <0x38 0x2c> */ | |||||
PLIST(l4ls_clkctrl_38_0) = { "dpll_per_m2_div4_ck" }; /* am3.h UART6 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_4) = { "mmc_clk" }; /* am3.h MMC1 clkctrl, TRM 18.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_8) = { "l4ls_gclk" }; /* am3.h ELM clkctrl, TRM 7.4.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_c) = { "dpll_per_m2_div4_ck" }; /* am3.h I2C3 clkctrl, TRM 21.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_10) = { "dpll_per_m2_div4_ck" }; /* am3.h I2C2 clkctrl, TRM 21.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_14) = { "dpll_per_m2_div4_ck" }; /* am3.h SPI0 clkctrl, TRM 24.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_18) = { "dpll_per_m2_div4_ck" }; /* am3.h SPI1 clkctrl, TRM 24.2.2 */ | |||||
/* 1c, 20, 24 are not described in the TRM */ | |||||
//PLIST(l4ls_clkctrl_38_1c) = { NULL }; /* am3.h TRM ? */ | |||||
//PLIST(l4ls_clkctrl_38_20) = { NULL }; /* am3.h TRM ? */ | |||||
//PLIST(l4ls_clkctrl_38_24) = { NULL }; /* am3.h TRM ? */ | |||||
PLIST(l4ls_clkctrl_38_28) = { "l4ls_gclk" }; /* am3.h L4_LS clkctrl, TRM 8.1.12.1.19 */ | |||||
/* <0x6c 0x28> */ | |||||
PLIST(l4ls_clkctrl_38_34) = { "dpll_per_m2_div4_ck" }; /* am3.h UART2 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_38) = { "dpll_per_m2_div4_ck" }; /* am3.h UART3 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_3c) = { "dpll_per_m2_div4_ck" }; /* am3.h UART4 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_40) = { "dpll_per_m2_div4_ck" }; /* am3.h UART4 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_44) = { "dpll_per_m2_div4_ck" }; /* am3.h UART5 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_48) = { "timer7_fck@504" }; /* am3.h TIMER7 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_4c) = { "timer2_fck@508" }; /* am3.h TIMER2 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_50) = { "timer3_fck@50c" }; /* am3.h TIMER3 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_54) = { "timer4_fck@510" }; /* am3.h TIMER4 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_58) = { "rng_fck" }; /* am3.h RNG clkctrl, TRM doesnt describe the rng, rng_fck only from the am33xx-clocks.dtsi */ | |||||
/* <0xac 0xc> */ | |||||
PLIST(l4ls_clkctrl_38_74) = { "l4ls_gclk" }; /* am3.h GPIO2 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_75) = { "clk_32768_ck" }; /* am3.h GPIO2 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_78) = { "l4ls_gclk" }; /* am3.h GPIO3 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_79) = { "clk_32768_ck" }; /* am3.h GPIO3 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_7c) = { "l4ls_gclk" }; /* am3.h GPIO4 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_7d) = { "clk_32768_ck" }; /* am3.h GPIO4 clkctrl, TRM 25.2.2 */ | |||||
/* <0xc0 0x1c> */ | |||||
PLIST(l4ls_clkctrl_38_88) = { "dcan0_fck" }; /* am3.h D_CAN0 clkctrl, TRM 23.2.2 */ | |||||
PLIST(l4ls_clkctrl_38_8c) = { "dcan1_fck" }; /* am3.h D_CAN1 clkctrl, TRM 23.2.2 */ | |||||
/* 90 not described in am3.h */ | |||||
//PLIST(l4ls_clkctrl_38_90) = { NULL }; /* am3.h */ | |||||
PLIST(l4ls_clkctrl_38_94) = { "l4ls_gclk" }; /* am3.h EPWMMS1 clkctrl, TRM 15.1.2.3 */ | |||||
/* 98 not described in am3.h */ | |||||
//PLIST(l4ls_clkctrl_38_98) = { NULL }; /* am3.h */ | |||||
PLIST(l4ls_clkctrl_38_9c) = { "l4ls_gclk" }; /* am3.h EPWMMS0 clkctrl, TRM 15.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_a0) = { "l4ls_gclk" }; /* am3.h EPWMMS2 clkctrl, TRM 15.1.2.3 */ | |||||
/* <0xec 0xc> */ | |||||
PLIST(l4ls_clkctrl_38_b4) = { "timer5_fck@518" }; /* am3.h TIMER5 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_b8) = { "timer6_fck@51c" }; /* am3.h TIMER6 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4ls_clkctrl_38_bc) = { "mmc_clk" }; /* am3.h MMC2 clkctrl, TRM 18.2.2 */ | |||||
/* <0xd4 0x8> */ | |||||
PLIST(l4ls_clkctrl_38_d4) = { "l4ls_gclk" }; /* am3.h SPINLOCK clkctrl, TRM 8.1.12.1.48 "SPINLOCK clocks" */ | |||||
PLIST(l4ls_clkctrl_38_d8) = { "l4ls_gclk" }; /* am3.h MAILBOX clkctrl, TRM 17.1.1.2 */ | |||||
/* <0x130 0x4> */ | |||||
PLIST(l4ls_clkctrl_38_f8) = { "l4ls_gclk" }; /* am3.h OCPWP clkctrl, TRM 8.1.12.1.53 "OCPWP clocks" */ | |||||
/* reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4> */ | |||||
/* <0x1c 0x4> */ | |||||
PLIST(l3s_clkctrl_1c_0) = { "usbotg_fck@47c" }; /* am3.h USB_OTG_HS clkctrl, TRM 16.1.2 fig 16-1 */ | |||||
/* <0x30 0x8> */ | |||||
PLIST(l3s_clkctrl_1c_14) = { "l3s_gclk" }; /* am3.h GPMC clkctrl, TRM 7.1.2.2 */ | |||||
PLIST(l3s_clkctrl_1c_18) = { "mcasp0_fck" }; /* am3.h MCASP0 clkctrl, TRM 22.2.2 */ | |||||
/* <0x68 0x4> */ | |||||
PLIST(l3s_clkctrl_1c_4c) = { "mcasp1_fck" }; /* am3.h MCASP1 clkctrl, TRM 22.2.2 */ | |||||
/* <0xf8 0x4> */ | |||||
PLIST(l3s_clkctrl_1c_dc) = { "mmc_clk" }; /* am3.h MMC3 clkctrl, TRM 18.2.2 */ | |||||
/* reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; */ | |||||
/* <0x24 0xc> */ | |||||
PLIST(l3_clkctrl_24_0) = { "l3_gclk" }; /* am3.h TPTC0 clkctrl, TRM 11.2.2.2 */ | |||||
PLIST(l3_clkctrl_24_4) = { "dpll_ddr_m2_div2_ck" }; /* am3.h EMIF clkctrl, TRM 7.3.2.2 */ | |||||
PLIST(l3_clkctrl_24_8) = { "l3_gclk" }; /* am3.h OCMCRAM clkctrl, TRM 7.2.2.2 */ | |||||
/* <0x94 0x10> */ | |||||
PLIST(l3_clkctrl_24_70) = { "aes0_fck" }; /* am3.h AES clkctrl, not in TRM, derived from am33xx-clocks.dtsi */ | |||||
//PLIST(l3_clkctrl_24_74) = { NULL }; /* am3.h ?? clkctrl, TRM ??? */ | |||||
//PLIST(l3_clkctrl_24_78) = { NULL }; /* am3.h ?? clkctrl, TRM ???? */ | |||||
PLIST(l3_clkctrl_24_7c) = { "l3_gclk" }; /* am3.h SHAM clkctrl, not in TRM, assume l3_gclk */ | |||||
/* <0xbc 0x4> */ | |||||
PLIST(l3_clkctrl_24_98) = { "l3_gclk" }; /* am3.h TPCC clkctrl, TRM 11.2.1.2 */ | |||||
/* <0xdc 0x8> */ | |||||
PLIST(l3_clkctrl_24_b8) = { "l3_gclk" }; /* am3.h L3 INSTR clkctrl, TRM 8.1.12.1.38 "L3 INSTR clocks" */ | |||||
PLIST(l3_clkctrl_24_bc) = { "l3_gclk" }; /* am3.h L3 Main clkctrl, TRM 18.1.12.1.39 "L3 interconnect clocks" */ | |||||
/* <0xfc 0x8> */ | |||||
PLIST(l3_clkctrl_24_d8) = { "l3_gclk" }; /* am3.h TPTC1 clkctrl, TRM 11.2.2.2 */ | |||||
PLIST(l3_clkctrl_24_dc) = { "l3_gclk" }; /* am3.h TPTC2 clkctrl, TRM 11.2.2.2 */ | |||||
/* reg = <0x120 0x4>; */ | |||||
PLIST(l4hs_clkctrl_120_0) = { "l4hs_gclk" }; /* am3.h L4HS clkctrl, TRM 8.1.12.1.50 */ | |||||
/* reg = <0xe8 0x4>; */ | |||||
PLIST(pruss_ocp_clkctrl_e8_0) = { "pruss_ocp_gclk@530" }; /* am3.h ocp pruss clkctrl, TRM 4.2.2 */ | |||||
/* reg = <0x0 0x18>; */ | |||||
#if 0 | |||||
PLIST(cpsw_125mhz_clkctrl_0_0) = { NULL }; /* am3.h Not mentioned in TRM, TRM 14.2.2 */ | |||||
PLIST(cpsw_125mhz_clkctrl_0_4) = { NULL }; /* am3.h Not mentioned in TRM, TRM 14.2.2 */ | |||||
PLIST(cpsw_125mhz_clkctrl_0_8) = { NULL }; /* am3.h Not mentioned in TRM, TRM 14.2.2 */ | |||||
PLIST(cpsw_125mhz_clkctrl_0_c) = { NULL }; /* am3.h Not mentioned in TRM, TRM 14.2.2 */ | |||||
PLIST(cpsw_125mhz_clkctrl_0_10) = { NULL }; /* am3.h Not mentioned in TRM, TRM 14.2.2 */ | |||||
#endif | |||||
PLIST(cpsw_125mhz_clkctrl_0_14) = { "cpsw_125mhz_gclk" }; /* am3.h cpsw 125 mhz cpgmaco clkctrl, TRM 14.2.2 */ | |||||
/* reg = <0x18 0x4>; */ | |||||
PLIST(lcdc_clkctrl_18_0) = { "lcd_gclk@534" }; /* am3.h lcdc clkctrl, TRM 13.2.2 */ | |||||
/* reg = <0x14c 0x4>; */ | |||||
PLIST(clk_24mhz_clkctrl_14c_0) = { "clkdiv32k_ck" }; /* am3.h clkdiv32k clkctrl, TRM 8.1.12.1.57 */ | |||||
/* reg = <0x0 0x10>, <0xb4 0x24>; */ | |||||
/* <0x0 0x10> */ | |||||
//PLIST(l4_wkup_clkctrl_0_0) = { NULL }; /* am3.h clkstctrl, TRM 8.1.12.2.1 */ | |||||
PLIST(l4_wkup_clkctrl_0_4) = { "mmc_clk" }; /* am3.h control clkctrl, TRM 18.2.2 */ | |||||
PLIST(l4_wkup_clkctrl_0_8) = { "dpll_core_m4_div2_ck" }; /* am3.h gpio1 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4_wkup_clkctrl_0_9) = { "gpio0_dbclk_mux_ck@53c" }; /* am3.h gpio1 clkctrl, TRM 25.2.2 */ | |||||
PLIST(l4_wkup_clkctrl_0_c) = { "mmc_clk" }; /* am3.h L4 wkup clkctrl, TRM 18.2.2 */ | |||||
/* <0xb4 0x24> */ | |||||
PLIST(l4_wkup_clkctrl_0_b4) = { "dpll_per_m2_div4_wkupdm_ck" }; /* am3.h uart1 clkctrl, TRM 19.2.2 */ | |||||
PLIST(l4_wkup_clkctrl_0_b8) = { "dpll_per_m2_div4_wkupdm_ck" }; /* am3.h i2c1 wkup clkctrl, TRM 21.2.2 */ | |||||
PLIST(l4_wkup_clkctrl_0_bc) = { "adc_tsc_fck" }; /* am3.h adc tsc clkctrl, TRM 12.2.2 */ | |||||
PLIST(l4_wkup_clkctrl_0_c0) = { "smartreflex0_fck" }; /* am3.h smartreflex0 clkctrl, TRM 8.1.12.2.49 */ | |||||
PLIST(l4_wkup_clkctrl_0_c4) = { "timer1_fck@528" }; /* am3.h timer1 clkctrl, TRM 20.1.2.3 */ | |||||
PLIST(l4_wkup_clkctrl_0_c8) = { "smartreflex1_fck" }; /* am3.h smartreflex1 clkctrl, TRM 8.1.12.2.51 */ | |||||
//PLIST(l4_wkup_clkctrl_0_cc) = { NULL }; /* am3.h l4_wkup_aon_clkstctrl, TRM 8.1.12.2.52 */ | |||||
//PLIST(l4_wkup_clkctrl_0_d0) = { NULL }; /* am3.h ??? clkctrl, not in TRM */ | |||||
PLIST(l4_wkup_clkctrl_0_d4) = { "wdt1_fck@538" }; /* am3.h wd timer2 clkctrl, TRM 20.4.2.2 */ | |||||
/* reg = <0x14 0x4>; */ | |||||
//PLIST(l3_aon_clkctrl_14_0) = { NULL }; /* am3.h debugss clkctrl, TRM 8.1.12.2.6 multiple sub clocks - todo */ | |||||
/* reg = <0xb0 0x4>; */ | |||||
//PLIST(l4_wkup_aon_wkup_m3_clkctrl_b0_0) = { NULL }; /* am3.h l4 wkup aon wkup m3 clkctrl, TRM 8.1.12.2.45 */ | |||||
/* reg = <0x0 0x8>; */ | |||||
//PLIST(mpu_clkctrl_0_0) = { NULL }; /* am3.h mpu clkstctrl, TRM 8.1.12.4.1 */ | |||||
PLIST(mpu_clkctrl_0_4) = { "dpll_mpu_ck@488" }; /* am3.h mpu clkctrl, TRM 8.1.12.4.2 / 3.1.3 */ | |||||
/* reg = <0x0 0x4>; */ | |||||
PLIST(l4_rtc_clkctrl_0_0) = { "clk_32768_ck" }; /* am3.h RTC clkctrl, TRM 20.3.2.2 */ | |||||
/* reg = <0x0 0x8>; */ | |||||
//PLIST(gfx_l3_clkctrl_0_0) = { NULL }; /* am3.h L3 GFX clkctrl, TRM 5.1.2 */ | |||||
PLIST(gfx_l3_clkctrl_0_4) = { "gfx_fck_div_ck@52c" }; /* am3.h L3 GFX clkctrl, TRM 5.1.2 */ | |||||
/* reg = <0x0 0x24>; */ | |||||
#if 0 | |||||
PLIST(l4_cefuse_clkctrl_0_0) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_4) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_8) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_c) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_10) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_14) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_18) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_1c) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
PLIST(l4_cefuse_clkctrl_0_20) = { NULL }; /* am3.h cefuse clkctrl, TRM 8.1.12.8.2 */ | |||||
#endif | |||||
static struct parent_lookup_table clkctrl_parent_table[] = { | |||||
/* reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; | |||||
*/ | |||||
/* <0x38 0x2c> */ | |||||
{ "l4ls-clkctrl@38_0", nitems(l4ls_clkctrl_38_0), l4ls_clkctrl_38_0 }, | |||||
{ "l4ls-clkctrl@38_4", nitems(l4ls_clkctrl_38_4), l4ls_clkctrl_38_4 }, | |||||
{ "l4ls-clkctrl@38_8", nitems(l4ls_clkctrl_38_8), l4ls_clkctrl_38_8 }, | |||||
{ "l4ls-clkctrl@38_c", nitems(l4ls_clkctrl_38_c), l4ls_clkctrl_38_c }, | |||||
{ "l4ls-clkctrl@38_10", nitems(l4ls_clkctrl_38_10), l4ls_clkctrl_38_10 }, | |||||
{ "l4ls-clkctrl@38_14", nitems(l4ls_clkctrl_38_14), l4ls_clkctrl_38_14 }, | |||||
{ "l4ls-clkctrl@38_18", nitems(l4ls_clkctrl_38_18), l4ls_clkctrl_38_18 }, | |||||
{ "l4ls-clkctrl@38_1c", 0, NULL }, | |||||
{ "l4ls-clkctrl@38_20", 0, NULL }, | |||||
{ "l4ls-clkctrl@38_24", 0, NULL }, | |||||
{ "l4ls-clkctrl@38_28", nitems(l4ls_clkctrl_38_28), l4ls_clkctrl_38_28 }, | |||||
/* <0x6c 0x28> */ | |||||
{ "l4ls-clkctrl@38_34", nitems(l4ls_clkctrl_38_34), l4ls_clkctrl_38_34 }, | |||||
{ "l4ls-clkctrl@38_38", nitems(l4ls_clkctrl_38_38), l4ls_clkctrl_38_38 }, | |||||
{ "l4ls-clkctrl@38_3c", nitems(l4ls_clkctrl_38_3c), l4ls_clkctrl_38_3c }, | |||||
{ "l4ls-clkctrl@38_40", nitems(l4ls_clkctrl_38_40), l4ls_clkctrl_38_40 }, | |||||
{ "l4ls-clkctrl@38_44", nitems(l4ls_clkctrl_38_44), l4ls_clkctrl_38_44 }, | |||||
{ "l4ls-clkctrl@38_48", nitems(l4ls_clkctrl_38_48), l4ls_clkctrl_38_48 }, | |||||
{ "l4ls-clkctrl@38_4c", nitems(l4ls_clkctrl_38_4c), l4ls_clkctrl_38_4c }, | |||||
{ "l4ls-clkctrl@38_50", nitems(l4ls_clkctrl_38_50), l4ls_clkctrl_38_50 }, | |||||
{ "l4ls-clkctrl@38_54", nitems(l4ls_clkctrl_38_54), l4ls_clkctrl_38_54 }, | |||||
{ "l4ls-clkctrl@38_58", nitems(l4ls_clkctrl_38_58), l4ls_clkctrl_38_58 }, | |||||
/* <0xac 0xc> */ | |||||
{ "l4ls-clkctrl@38_74", nitems(l4ls_clkctrl_38_74), l4ls_clkctrl_38_74 }, | |||||
{ "l4ls-clkctrl@38_75", nitems(l4ls_clkctrl_38_75), l4ls_clkctrl_38_75 }, | |||||
{ "l4ls-clkctrl@38_78", nitems(l4ls_clkctrl_38_78), l4ls_clkctrl_38_78 }, | |||||
{ "l4ls-clkctrl@38_79", nitems(l4ls_clkctrl_38_79), l4ls_clkctrl_38_79 }, | |||||
{ "l4ls-clkctrl@38_7c", nitems(l4ls_clkctrl_38_7c), l4ls_clkctrl_38_7c }, | |||||
{ "l4ls-clkctrl@38_7d", nitems(l4ls_clkctrl_38_7d), l4ls_clkctrl_38_7d }, | |||||
/* <0xc0 0x1c> */ | |||||
{ "l4ls-clkctrl@38_88", nitems(l4ls_clkctrl_38_88), l4ls_clkctrl_38_88 }, | |||||
{ "l4ls-clkctrl@38_8c", nitems(l4ls_clkctrl_38_8c), l4ls_clkctrl_38_8c }, | |||||
{ "l4ls-clkctrl@38_90", 0, NULL }, | |||||
{ "l4ls-clkctrl@38_94", nitems(l4ls_clkctrl_38_94), l4ls_clkctrl_38_94 }, | |||||
{ "l4ls-clkctrl@38_98", 0, NULL }, | |||||
{ "l4ls-clkctrl@38_9c", nitems(l4ls_clkctrl_38_9c), l4ls_clkctrl_38_9c }, | |||||
{ "l4ls-clkctrl@38_a0", nitems(l4ls_clkctrl_38_a0), l4ls_clkctrl_38_a0 }, | |||||
/* <0xec 0xc> */ | |||||
{ "l4ls-clkctrl@38_b4", nitems(l4ls_clkctrl_38_b4), l4ls_clkctrl_38_b4 }, | |||||
{ "l4ls-clkctrl@38_b8", nitems(l4ls_clkctrl_38_b8), l4ls_clkctrl_38_b8 }, | |||||
{ "l4ls-clkctrl@38_bc", nitems(l4ls_clkctrl_38_bc), l4ls_clkctrl_38_bc }, | |||||
/* <0xd4 0x8> */ | |||||
{ "l4ls-clkctrl@38_d4", nitems(l4ls_clkctrl_38_d4), l4ls_clkctrl_38_d4 }, | |||||
{ "l4ls-clkctrl@38_d8", nitems(l4ls_clkctrl_38_d8), l4ls_clkctrl_38_d8 }, | |||||
/* <0x130 0x4> */ | |||||
{ "l4ls-clkctrl@38_f8", nitems(l4ls_clkctrl_38_f8), l4ls_clkctrl_38_f8 }, | |||||
/* reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4> */ | |||||
/* <0x1c 0x4> */ | |||||
{ "l3s-clkctrl@1c_0", nitems(l3s_clkctrl_1c_0), l3s_clkctrl_1c_0 }, | |||||
/* <0x30 0x8> */ | |||||
{ "l3s-clkctrl@1c_14", nitems(l3s_clkctrl_1c_14), l3s_clkctrl_1c_14 }, | |||||
{ "l3s-clkctrl@1c_18", nitems(l3s_clkctrl_1c_18), l3s_clkctrl_1c_18 }, | |||||
/* <0x68 0x4> */ | |||||
{ "l3s-clkctrl@1c_4c", nitems(l3s_clkctrl_1c_4c), l3s_clkctrl_1c_4c }, | |||||
/* <0xf8 0x4> */ | |||||
{ "l3s-clkctrl@1c_dc", nitems(l3s_clkctrl_1c_dc), l3s_clkctrl_1c_dc }, | |||||
/* reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; */ | |||||
/* <0x24 0xc> */ | |||||
{ "l3-clkctrl@24_0", nitems(l3_clkctrl_24_0), l3_clkctrl_24_0 }, | |||||
{ "l3-clkctrl@24_4", nitems(l3_clkctrl_24_4), l3_clkctrl_24_4 }, | |||||
{ "l3-clkctrl@24_8", nitems(l3_clkctrl_24_8), l3_clkctrl_24_8 }, | |||||
/* <0x94 0x10> */ | |||||
{ "l3-clkctrl@24_70", nitems(l3_clkctrl_24_70), l3_clkctrl_24_70 }, | |||||
{ "l3-clkctrl@24_74", 0, NULL }, | |||||
{ "l3-clkctrl@24_78", 0, NULL }, | |||||
{ "l3-clkctrl@24_7c", nitems(l3_clkctrl_24_7c), l3_clkctrl_24_7c }, | |||||
/* <0xbc 0x4> */ | |||||
{ "l3-clkctrl@24_98", nitems(l3_clkctrl_24_98), l3_clkctrl_24_98 }, | |||||
/* <0xdc 0x8> */ | |||||
{ "l3-clkctrl@24_b8", nitems(l3_clkctrl_24_b8), l3_clkctrl_24_b8 }, | |||||
{ "l3-clkctrl@24_bc", nitems(l3_clkctrl_24_bc), l3_clkctrl_24_bc }, | |||||
/* <0xfc 0x8> */ | |||||
{ "l3-clkctrl@24_d8", nitems(l3_clkctrl_24_d8), l3_clkctrl_24_d8 }, | |||||
{ "l3-clkctrl@24_dc", nitems(l3_clkctrl_24_dc), l3_clkctrl_24_dc }, | |||||
/* reg = <0x120 0x4>; */ | |||||
{ "l4hs-clkctrl@120_0", nitems(l4hs_clkctrl_120_0), l4hs_clkctrl_120_0 }, | |||||
/* reg = <0xe8 0x4>; */ | |||||
{ "pruss-ocp-clkctrl@e8_0", nitems(pruss_ocp_clkctrl_e8_0), pruss_ocp_clkctrl_e8_0 }, | |||||
/* reg = <0x0 0x18>; */ | |||||
{ "cpsw-125mhz-clkctrl@0_0", 0, NULL }, | |||||
{ "cpsw-125mhz-clkctrl@0_4", 0, NULL }, | |||||
{ "cpsw-125mhz-clkctrl@0_8", 0, NULL }, | |||||
{ "cpsw-125mhz-clkctrl@0_c", 0, NULL }, | |||||
{ "cpsw-125mhz-clkctrl@0_10", 0, NULL }, | |||||
{ "cpsw-125mhz-clkctrl@0_14", nitems(cpsw_125mhz_clkctrl_0_14), cpsw_125mhz_clkctrl_0_14 }, | |||||
/* reg = <0x18 0x4>; */ | |||||
{ "lcdc-clkctrl@18_0", nitems(lcdc_clkctrl_18_0), lcdc_clkctrl_18_0 }, | |||||
/* reg = <0x14c 0x4>; */ | |||||
{ "clk-24mhz-clkctrl@14c_0", nitems(clk_24mhz_clkctrl_14c_0), clk_24mhz_clkctrl_14c_0 }, | |||||
/* reg = <0x0 0x10>, <0xb4 0x24>; */ | |||||
/* <0x0 0x10> */ | |||||
{ "l4-wkup-clkctrl@0_0", 0, NULL }, | |||||
{ "l4-wkup-clkctrl@0_4", nitems(l4_wkup_clkctrl_0_4), l4_wkup_clkctrl_0_4 }, | |||||
{ "l4-wkup-clkctrl@0_8", nitems(l4_wkup_clkctrl_0_8), l4_wkup_clkctrl_0_8 }, | |||||
{ "l4-wkup-clkctrl@0_9", nitems(l4_wkup_clkctrl_0_9), l4_wkup_clkctrl_0_9 }, | |||||
{ "l4-wkup-clkctrl@0_c", nitems(l4_wkup_clkctrl_0_c), l4_wkup_clkctrl_0_c }, | |||||
/* <0xb4 0x24> */ | |||||
{ "l4-wkup-clkctrl@0_b4", nitems(l4_wkup_clkctrl_0_b4), l4_wkup_clkctrl_0_b4 }, | |||||
{ "l4-wkup-clkctrl@0_b8", nitems(l4_wkup_clkctrl_0_b8), l4_wkup_clkctrl_0_b8 }, | |||||
{ "l4-wkup-clkctrl@0_bc", nitems(l4_wkup_clkctrl_0_bc), l4_wkup_clkctrl_0_bc }, | |||||
{ "l4-wkup-clkctrl@0_c0", nitems(l4_wkup_clkctrl_0_c0), l4_wkup_clkctrl_0_c0 }, | |||||
{ "l4-wkup-clkctrl@0_c4", nitems(l4_wkup_clkctrl_0_c4), l4_wkup_clkctrl_0_c4 }, | |||||
{ "l4-wkup-clkctrl@0_c8", nitems(l4_wkup_clkctrl_0_c8), l4_wkup_clkctrl_0_c8 }, | |||||
{ "l4-wkup-clkctrl@0_cc", 0, NULL }, | |||||
{ "l4-wkup-clkctrl@0_d0", 0, NULL }, | |||||
{ "l4-wkup-clkctrl@0_d4", nitems(l4_wkup_clkctrl_0_d4), l4_wkup_clkctrl_0_d4 }, | |||||
/* reg = <0x14 0x4>; */ | |||||
{ "l3-aon-clkctrl@14_0", 0, NULL }, | |||||
/* reg = <0xb0 0x4>; */ | |||||
{ "l4-wkup-aon-clkctrl@b0_0", 0, NULL }, | |||||
/* reg = <0x0 0x8>; */ | |||||
{ "mpu-clkctrl@0_0", 0, NULL }, | |||||
{ "mpu-clkctrl@0_4", nitems(mpu_clkctrl_0_4), mpu_clkctrl_0_4 }, | |||||
/* reg = <0x0 0x4>; */ | |||||
{ "l4-rtc-clkctrl@0_0", nitems(l4_rtc_clkctrl_0_0), l4_rtc_clkctrl_0_0 }, | |||||
/* reg = <0x0 0x8>; */ | |||||
{ "gfx-l3-clkctrl@0_0", 0, NULL }, | |||||
{ "gfx-l3-clkctrl@0_4", nitems(gfx_l3_clkctrl_0_4), gfx_l3_clkctrl_0_4 }, | |||||
/* reg = <0x0 0x24>; */ | |||||
{ "l4-cefuse-clkctrl@0_0", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_4", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_8", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_c", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_10", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_14", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_18", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_1c", 0, NULL }, | |||||
{ "l4-cefuse-clkctrl@0_20", 0, NULL }, | |||||
}; | |||||
static int ti_clkctrl_probe(device_t dev); | static int ti_clkctrl_probe(device_t dev); | ||||
static int ti_clkctrl_attach(device_t dev); | static int ti_clkctrl_attach(device_t dev); | ||||
static int ti_clkctrl_detach(device_t dev); | static int ti_clkctrl_detach(device_t dev); | ||||
int clkctrl_ofw_map(struct clkdom *clkdom, uint32_t ncells, | int clkctrl_ofw_map(struct clkdom *clkdom, uint32_t ncells, | ||||
phandle_t *cells, struct clknode **clk); | phandle_t *cells, struct clknode **clk); | ||||
static int | static int | ||||
create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, | create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, | ||||
uint64_t parent_offset, const char *org_name, bool special_gdbclk_reg); | uint64_t parent_offset, const char *org_name, bool special_gdbclk_reg); | ||||
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines | default: | ||||
break; | break; | ||||
} | } | ||||
/* reg property has a pair of (base address, length) */ | /* reg property has a pair of (base address, length) */ | ||||
for (index = 0; index < num_reg; index += 2) { | for (index = 0; index < num_reg; index += 2) { | ||||
for (reg_offset = 0; reg_offset < reg[index+1]; reg_offset += sizeof(cell_t)) { | for (reg_offset = 0; reg_offset < reg[index+1]; reg_offset += sizeof(cell_t)) { | ||||
err = create_clkctrl(sc, reg, index, reg_offset, parent_offset, | err = create_clkctrl(sc, reg, index, reg_offset, parent_offset, | ||||
org_name, false); | org_name, false); | ||||
if (err) | if (err != 0) | ||||
goto cleanup; | goto cleanup; | ||||
/* Create special clkctrl for GDBCLK in GPIO registers */ | /* Create special clkctrl for GDBCLK in GPIO registers */ | ||||
switch (special_reg) { | switch (special_reg) { | ||||
case NO_SPECIAL_REG: | case NO_SPECIAL_REG: | ||||
break; | break; | ||||
case L4LS_CLKCTRL_38: | case L4LS_CLKCTRL_38: | ||||
reg_address = reg[index] + reg_offset-reg[0]; | reg_address = reg[index] + reg_offset-reg[0]; | ||||
if (reg_address == 0x74 || | if (reg_address == 0x74 || | ||||
reg_address == 0x78 || | reg_address == 0x78 || | ||||
reg_address == 0x7C) | reg_address == 0x7C) | ||||
{ | { | ||||
err = create_clkctrl(sc, reg, index, reg_offset, | err = create_clkctrl(sc, reg, index, reg_offset, | ||||
parent_offset, org_name, true); | parent_offset, org_name, true); | ||||
if (err) | if (err != 0) | ||||
goto cleanup; | goto cleanup; | ||||
} | } | ||||
break; | break; | ||||
case L4_WKUP_CLKCTRL_0: | case L4_WKUP_CLKCTRL_0: | ||||
reg_address = reg[index] + reg_offset - reg[0]; | reg_address = reg[index] + reg_offset - reg[0]; | ||||
if (reg_address == 0x8) | if (reg_address == 0x8) | ||||
{ | { | ||||
err = create_clkctrl(sc, reg, index, reg_offset, | err = create_clkctrl(sc, reg, index, reg_offset, | ||||
parent_offset, org_name, true); | parent_offset, org_name, true); | ||||
if (err) | if (err != 0) | ||||
goto cleanup; | goto cleanup; | ||||
} | } | ||||
break; | break; | ||||
} /* switch (special_reg) */ | } /* switch (special_reg) */ | ||||
} /* inner for */ | } /* inner for */ | ||||
} /* for */ | } /* for */ | ||||
err = clkdom_finit(sc->clkdom); | err = clkdom_finit(sc->clkdom); | ||||
if (err) { | if (err != 0) { | ||||
DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err); | DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err); | ||||
err = ENXIO; | err = ENXIO; | ||||
goto cleanup; | goto cleanup; | ||||
} | } | ||||
cleanup: | cleanup: | ||||
OF_prop_free(__DECONST(char *, org_name)); | OF_prop_free(__DECONST(char *, org_name)); | ||||
free(reg, M_DEVBUF); | free(reg, M_DEVBUF); | ||||
if (err) | if (err != 0) | ||||
return (err); | return (err); | ||||
return (bus_generic_attach(dev)); | return (bus_generic_attach(dev)); | ||||
} | } | ||||
static int | static int | ||||
ti_clkctrl_detach(device_t dev) | ti_clkctrl_detach(device_t dev) | ||||
{ | { | ||||
Show All 25 Lines | clkctrl_ofw_map(struct clkdom *clkdom, uint32_t ncells, | ||||
return (0); | return (0); | ||||
} | } | ||||
static int | static int | ||||
create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, | create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, | ||||
uint64_t parent_offset, const char *org_name, bool special_gdbclk_reg) { | uint64_t parent_offset, const char *org_name, bool special_gdbclk_reg) { | ||||
struct ti_clk_clkctrl_def def; | struct ti_clk_clkctrl_def def; | ||||
char *name; | char *node_name; | ||||
size_t name_len; | size_t name_len; | ||||
int err; | int err, p_index=0; | ||||
name_len = strlen(org_name) + 1 + 5; /* 5 = _xxxx */ | name_len = strlen(org_name) + 1 + 5; /* 5 = _xxxx */ | ||||
name = malloc(name_len, M_OFWPROP, M_WAITOK); | node_name = malloc(name_len, M_OFWPROP, M_WAITOK); | ||||
/* | /* | ||||
* Check out XX_CLKCTRL-INDEX(offset)-macro dance in | * Check out XX_CLKCTRL-INDEX(offset)-macro dance in | ||||
* sys/gnu/dts/dts/include/dt-bindings/clock/am3.h | * sys/gnu/dts/dts/include/dt-bindings/clock/am3.h | ||||
* sys/gnu/dts/dts/include/dt-bindings/clock/am4.h | * sys/gnu/dts/dts/include/dt-bindings/clock/am4.h | ||||
* sys/gnu/dts/dts/include/dt-bindings/clock/dra7.h | * sys/gnu/dts/dts/include/dt-bindings/clock/dra7.h | ||||
* reg[0] are in practice the same as the offset described in the dts. | * reg[0] are in practice the same as the offset described in the dts. | ||||
*/ | */ | ||||
/* special_gdbclk_reg are 0 or 1 */ | /* special_gdbclk_reg are 0 or 1 */ | ||||
def.clkdef.id = reg[index] + reg_offset - reg[0] + special_gdbclk_reg; | def.clkdef.id = reg[index] + reg_offset - reg[0] + special_gdbclk_reg; | ||||
def.register_offset = parent_offset + reg[index] + reg_offset; | def.register_offset = parent_offset + reg[index] + reg_offset; | ||||
/* Indicate this clkctrl is special and dont use IDLEST/MODULEMODE */ | /* Indicate this clkctrl is special and dont use IDLEST/MODULEMODE */ | ||||
def.gdbclk = special_gdbclk_reg; | def.gdbclk = special_gdbclk_reg; | ||||
/* Make up an uniq name in the namespace for each clkctrl */ | /* Make up an uniq name in the namespace for each clkctrl */ | ||||
snprintf(name, name_len, "%s_%x", | snprintf(node_name, name_len, "%s_%x", | ||||
org_name, def.clkdef.id); | org_name, def.clkdef.id); | ||||
def.clkdef.name = (const char *) name; | |||||
DPRINTF(sc->dev, "ti_clkctrl_attach: reg[%d]: %s %x\n", | DPRINTF(sc->dev, "ti_clkctrl_attach: reg[%d]: %s %x\n", | ||||
index, def.clkdef.name, def.clkdef.id); | index, node_name, def.clkdef.id); | ||||
/* No parent name */ | /* Find parent in lookup table */ | ||||
def.clkdef.parent_cnt = 0; | for (p_index = 0; p_index < nitems(clkctrl_parent_table); p_index++) { | ||||
if (strcmp(node_name, clkctrl_parent_table[p_index].node_name) == 0) | |||||
break; | |||||
} | |||||
/* set flags */ | if (p_index == nitems(clkctrl_parent_table)) | ||||
def.clkdef.flags = 0x0; | panic("Cant find clock %s\n", node_name); | ||||
DPRINTF(sc->dev, "%s at clkctrl_parent_table[%d] parent_cnt %d \n", | |||||
node_name, p_index, clkctrl_parent_table[p_index].parent_cnt); | |||||
/* set flags and name */ | |||||
def.clkdef.flags = CLK_NODE_STATIC_STRINGS; | |||||
def.clkdef.name = clkctrl_parent_table[p_index].node_name; | |||||
/* Handle parents */ | |||||
def.clkdef.parent_cnt = clkctrl_parent_table[p_index].parent_cnt; | |||||
def.clkdef.parent_names = clkctrl_parent_table[p_index].parent_names; | |||||
/* Register the clkctrl */ | /* Register the clkctrl */ | ||||
err = ti_clknode_clkctrl_register(sc->clkdom, &def); | err = ti_clknode_clkctrl_register(sc->clkdom, &def); | ||||
if (err) { | if (err != 0) { | ||||
DPRINTF(sc->dev, | DPRINTF(sc->dev, | ||||
"ti_clknode_clkctrl_register[%d:%d] failed %x\n", | "ti_clknode_clkctrl_register[%d:%d] failed %x\n", | ||||
index, reg_offset, err); | index, reg_offset, err); | ||||
err = ENXIO; | err = ENXIO; | ||||
} | } | ||||
OF_prop_free(name); | OF_prop_free(node_name); | ||||
return (err); | return (err); | ||||
} | } | ||||
static device_method_t ti_clkctrl_methods[] = { | static device_method_t ti_clkctrl_methods[] = { | ||||
/* Device interface */ | /* Device interface */ | ||||
DEVMETHOD(device_probe, ti_clkctrl_probe), | DEVMETHOD(device_probe, ti_clkctrl_probe), | ||||
DEVMETHOD(device_attach, ti_clkctrl_attach), | DEVMETHOD(device_attach, ti_clkctrl_attach), | ||||
DEVMETHOD(device_detach, ti_clkctrl_detach), | DEVMETHOD(device_detach, ti_clkctrl_detach), | ||||
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