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Differential D27797 Diff 82356 sys/dev/axgbe/xgbe-txrx.c

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sys/dev/axgbe/xgbe-txrx.c

Show First 20 Lines • Show All 373 Lines • ▼ Show 20 Linesaxgbe_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
struct xgbe_prv_data *pdata = &sc->pdata; struct xgbe_prv_data *pdata = &sc->pdata;
struct xgbe_channel *channel = pdata->channel[txqid]; struct xgbe_channel *channel = pdata->channel[txqid];
struct xgbe_ring *ring = channel->tx_ring; struct xgbe_ring *ring = channel->tx_ring;
struct xgbe_ring_data *rdata = XGBE_GET_DESC_DATA(ring, pidx); struct xgbe_ring_data *rdata = XGBE_GET_DESC_DATA(ring, pidx);
axgbe_printf(1, "--> %s: flush txq %d pidx %d cur %d dirty %d\n", axgbe_printf(1, "--> %s: flush txq %d pidx %d cur %d dirty %d\n",
__func__, txqid, pidx, ring->cur, ring->dirty); __func__, txqid, pidx, ring->cur, ring->dirty);
MPASS(ring->cur == pidx);
if (__predict_false(ring->cur != pidx)) {
axgbe_error("--> %s: cur(%d) ne pidx(%d)\n", __func__,
ring->cur, pidx);
}
wmb();
/* Ring Doorbell */ /* Ring Doorbell */
if (XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO) !=
lower_32_bits(rdata->rdata_paddr)) {
XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
lower_32_bits(rdata->rdata_paddr)); lower_32_bits(rdata->rdata_paddr));
} }
}
static int static int
axgbe_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear) axgbe_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
{ {
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg; struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
struct xgbe_hw_if *hw_if = &sc->pdata.hw_if; struct xgbe_hw_if *hw_if = &sc->pdata.hw_if;
struct xgbe_prv_data *pdata = &sc->pdata; struct xgbe_prv_data *pdata = &sc->pdata;
struct xgbe_channel *channel = pdata->channel[txqid]; struct xgbe_channel *channel = pdata->channel[txqid];
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesaxgbe_isc_rxd_refill(void *arg, if_rxd_update_t iru)
struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring *ring = channel->rx_ring;
struct xgbe_ring_data *rdata; struct xgbe_ring_data *rdata;
struct xgbe_ring_desc *rdesc; struct xgbe_ring_desc *rdesc;
unsigned int rx_usecs = pdata->rx_usecs; unsigned int rx_usecs = pdata->rx_usecs;
unsigned int rx_frames = pdata->rx_frames; unsigned int rx_frames = pdata->rx_frames;
unsigned int inte; unsigned int inte;
uint8_t count = iru->iru_count; uint8_t count = iru->iru_count;
int i, j; int i, j;
bool config_intr = false;
axgbe_printf(1, "--> %s: rxq %d fl %d pidx %d count %d ring cur %d " axgbe_printf(1, "--> %s: rxq %d fl %d pidx %d count %d ring cur %d "
"dirty %d\n", __func__, iru->iru_qsidx, iru->iru_flidx, "dirty %d\n", __func__, iru->iru_qsidx, iru->iru_flidx,
iru->iru_pidx, count, ring->cur, ring->dirty); iru->iru_pidx, count, ring->cur, ring->dirty);
for (i = iru->iru_pidx, j = 0 ; j < count ; i++, j++) { for (i = iru->iru_pidx, j = 0 ; j < count ; i++, j++) {
if (i == XGBE_RX_DESC_CNT_DEFAULT) if (i == sc->scctx->isc_nrxd[0])
i = 0; i = 0;
rdata = XGBE_GET_DESC_DATA(ring, i); rdata = XGBE_GET_DESC_DATA(ring, i);
rdesc = rdata->rdesc; rdesc = rdata->rdesc;
if (__predict_false(XGMAC_GET_BITS_LE(rdesc->desc3, if (__predict_false(XGMAC_GET_BITS_LE(rdesc->desc3,
RX_NORMAL_DESC3, OWN))) { RX_NORMAL_DESC3, OWN))) {
axgbe_error("%s: refill clash, cur %d dirty %d index %d" axgbe_error("%s: refill clash, cur %d dirty %d index %d"
"pidx %d\n", __func__, ring->cur, ring->dirty, j, i); "pidx %d\n", __func__, ring->cur, ring->dirty, j, i);
} }
/* Assuming split header is enabled */ if (pdata->sph_enable) {
vmaffioneUnsubmitted
Done
Inline Actions

This comment should go away.

vmaffione: This comment should go away.
if (iru->iru_flidx == 0) { if (iru->iru_flidx == 0) {
/* Fill header/buffer1 address */ /* Fill header/buffer1 address */
rdesc->desc0 = rdesc->desc0 =
cpu_to_le32(lower_32_bits(iru->iru_paddrs[j])); cpu_to_le32(lower_32_bits(iru->iru_paddrs[j]));
rdesc->desc1 = rdesc->desc1 =
cpu_to_le32(upper_32_bits(iru->iru_paddrs[j])); cpu_to_le32(upper_32_bits(iru->iru_paddrs[j]));
} else { } else {
/* Fill data/buffer2 address */ /* Fill data/buffer2 address */
rdesc->desc2 = rdesc->desc2 =
cpu_to_le32(lower_32_bits(iru->iru_paddrs[j])); cpu_to_le32(lower_32_bits(iru->iru_paddrs[j]));
rdesc->desc3 = rdesc->desc3 =
cpu_to_le32(upper_32_bits(iru->iru_paddrs[j])); cpu_to_le32(upper_32_bits(iru->iru_paddrs[j]));
config_intr = true;
}
} else {
/* Fill header/buffer1 address */
rdesc->desc0 = rdesc->desc2 =
cpu_to_le32(lower_32_bits(iru->iru_paddrs[j]));
rdesc->desc1 = rdesc->desc3 =
cpu_to_le32(upper_32_bits(iru->iru_paddrs[j]));
config_intr = true;
}
if (config_intr) {
vmaffioneUnsubmitted
Done
Inline Actions

If you are putting the same physical address in both address pointers, wouldn't the hardware use the same buffer twice (therefore overwriting?). Or maybe since sph is disabled, the second buffer pointer is actually never used by the hardware?

vmaffione: If you are putting the same physical address in both address pointers, wouldn't the hardware…
rajesh1.kumar_amd.comAuthorUnsubmitted
Done
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Yes. In this case, the second buffer pointer will not be used by hardware since the split header is disabled.

rajesh1.kumar_amd.com: Yes. In this case, the second buffer pointer will not be used by hardware since the split…
vmaffioneUnsubmitted
Done
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Ok, so we could perform less operations (and shorten the code):

`
rdesc->desc0 = rdesc->desc2 = ...;
rdesc->desc1 = rdesc->desc3 = ...;
`
vmaffione: Ok, so we could perform less operations (and shorten the code): ```` rdesc->desc0 = rdesc…
if (!rx_usecs && !rx_frames) { if (!rx_usecs && !rx_frames) {
/* No coalescing, interrupt for every descriptor */ /* No coalescing, interrupt for every descriptor */
inte = 1; inte = 1;
} else { } else {
/* Set interrupt based on Rx frame coalescing setting */ /* Set interrupt based on Rx frame coalescing setting */
if (rx_frames && if (rx_frames && !((ring->dirty + 1) % rx_frames))
!(((ring->dirty + 1) &(ring->rdesc_count - 1)) % rx_frames))
inte = 1; inte = 1;
else else
inte = 0; inte = 0;
} }
XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte);
XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
wmb(); wmb();
ring->dirty = ((ring->dirty + 1) & (ring->rdesc_count - 1)); ring->dirty = ((ring->dirty + 1) & (ring->rdesc_count - 1));
config_intr = false;
} }
} }
axgbe_printf(1, "<-- %s: rxq: %d cur: %d dirty: %d\n", __func__, axgbe_printf(1, "<-- %s: rxq: %d cur: %d dirty: %d\n", __func__,
channel->queue_index, ring->cur, ring->dirty); channel->queue_index, ring->cur, ring->dirty);
} }
static void static void
axgbe_isc_rxd_flush(void *arg, uint16_t qsidx, uint8_t flidx, qidx_t pidx) axgbe_isc_rxd_flush(void *arg, uint16_t qsidx, uint8_t flidx, qidx_t pidx)
{ {
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg; struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
struct xgbe_prv_data *pdata = &sc->pdata; struct xgbe_prv_data *pdata = &sc->pdata;
struct xgbe_channel *channel = pdata->channel[qsidx]; struct xgbe_channel *channel = pdata->channel[qsidx];
struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring *ring = channel->rx_ring;
struct xgbe_ring_data *rdata; struct xgbe_ring_data *rdata;
axgbe_printf(1, "--> %s: rxq %d fl %d pidx %d cur %d dirty %d\n", axgbe_printf(1, "--> %s: rxq %d fl %d pidx %d cur %d dirty %d\n",
__func__, qsidx, flidx, pidx, ring->cur, ring->dirty); __func__, qsidx, flidx, pidx, ring->cur, ring->dirty);
if (flidx == 1) {
rdata = XGBE_GET_DESC_DATA(ring, pidx); rdata = XGBE_GET_DESC_DATA(ring, pidx);
/*
* update RX descriptor tail pointer in hardware to indicate
* that new buffers are present in the allocated memory region
*/
if (!pdata->sph_enable || flidx == 1) {
XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
lower_32_bits(rdata->rdata_paddr)); lower_32_bits(rdata->rdata_paddr));
} }
vmaffioneUnsubmitted
Done
Inline Actions

We could avoid code duplication, by using a combined condition
if (!pdata->sph_enable || flidx == 1)

vmaffione: We could avoid code duplication, by using a combined condition `if (!pdata->sph_enable || flidx…
wmb();
} }
vmaffioneUnsubmitted
Done
Inline Actions

Out of curiosity: shouldn't the write memory barrier be executed only if we actually IOWRITE?

vmaffione: Out of curiosity: shouldn't the write memory barrier be executed only if we actually IOWRITE?
rajesh1.kumar_amd.comAuthorUnsubmitted
Done
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Removed it. As wmb is done already in rxd_refill.

rajesh1.kumar_amd.com: Removed it. As wmb is done already in rxd_refill.
rajesh1.kumar_amd.comAuthorUnsubmitted
Done
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Missed to mention. Inline with this, similar change has been done in txd_flush routine as well. Also removed an unwanted check in txd_flush routine.

rajesh1.kumar_amd.com: Missed to mention. Inline with this, similar change has been done in txd_flush routine as well.
static int static int
axgbe_isc_rxd_available(void *arg, uint16_t qsidx, qidx_t idx, qidx_t budget) axgbe_isc_rxd_available(void *arg, uint16_t qsidx, qidx_t idx, qidx_t budget)
{ {
struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg; struct axgbe_if_softc *sc = (struct axgbe_if_softc*)arg;
struct xgbe_prv_data *pdata = &sc->pdata; struct xgbe_prv_data *pdata = &sc->pdata;
struct xgbe_channel *channel = pdata->channel[qsidx]; struct xgbe_channel *channel = pdata->channel[qsidx];
struct xgbe_ring *ring = channel->rx_ring; struct xgbe_ring *ring = channel->rx_ring;
struct xgbe_ring_data *rdata; struct xgbe_ring_data *rdata;
struct xgbe_ring_desc *rdesc; struct xgbe_ring_desc *rdesc;
unsigned int cur; unsigned int cur;
int count; int count = 0;
uint8_t incomplete = 1, context_next = 0, running = 0; uint8_t incomplete = 1, context_next = 0, running = 0;
axgbe_printf(1, "--> %s: rxq %d idx %d budget %d cur %d dirty %d\n", axgbe_printf(1, "--> %s: rxq %d idx %d budget %d cur %d dirty %d\n",
__func__, qsidx, idx, budget, ring->cur, ring->dirty); __func__, qsidx, idx, budget, ring->cur, ring->dirty);
if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
axgbe_printf(0, "%s: Polling when XGBE_DOWN\n", __func__);
return (count);
}
cur = ring->cur; cur = ring->cur;
for (count = 0; count <= budget; ) { for (count = 0; count <= budget; ) {
rdata = XGBE_GET_DESC_DATA(ring, cur); rdata = XGBE_GET_DESC_DATA(ring, cur);
rdesc = rdata->rdesc; rdesc = rdata->rdesc;
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
break; break;
Show All 27 Linesaxgbe_isc_rxd_available(void *arg, uint16_t qsidx, qidx_t idx, qidx_t budget)
return (count); return (count);
} }
static unsigned int static unsigned int
xgbe_rx_buf1_len(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata, xgbe_rx_buf1_len(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata,
struct xgbe_packet_data *packet) struct xgbe_packet_data *packet)
{ {
unsigned int ret = 0;
if (pdata->sph_enable) {
/* Always zero if not the first descriptor */ /* Always zero if not the first descriptor */
if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST)) { if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, FIRST)) {
axgbe_printf(1, "%s: Not First\n", __func__); axgbe_printf(1, "%s: Not First\n", __func__);
return (0); return (0);
} }
}
/* First descriptor with split header, return header length */ /* First descriptor with split header, return header length */
if (rdata->rx.hdr_len) { if (rdata->rx.hdr_len) {
axgbe_printf(1, "%s: hdr_len %d\n", __func__, rdata->rx.hdr_len); axgbe_printf(1, "%s: hdr_len %d\n", __func__, rdata->rx.hdr_len);
return (rdata->rx.hdr_len); return (rdata->rx.hdr_len);
} }
/* First descriptor but not the last descriptor and no split header, /* First descriptor but not the last descriptor and no split header,
* so the full buffer was used * so the full buffer was used, 256 represents the hardcoded value of
* a max header split defined in the hardware
*/ */
if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) { if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) {
axgbe_printf(1, "%s: Not last %d\n", __func__, axgbe_printf(1, "%s: Not last %d\n", __func__,
pdata->rx_buf_size); pdata->rx_buf_size);
if (pdata->sph_enable) {
return (256); return (256);
} else {
return (pdata->rx_buf_size);
} }
}
/* First descriptor and last descriptor and no split header, so /* First descriptor and last descriptor and no split header, so
* calculate how much of the buffer was used * calculate how much of the buffer was used, we can return the
* segment length or the remaining bytes of the packet
*/ */
axgbe_printf(1, "%s: pkt_len %d buf_size %d\n", __func__, rdata->rx.len, axgbe_printf(1, "%s: pkt_len %d buf_size %d\n", __func__, rdata->rx.len,
pdata->rx_buf_size); pdata->rx_buf_size);
return (min_t(unsigned int, 256, rdata->rx.len)); if (pdata->sph_enable) {
ret = min_t(unsigned int, 256, rdata->rx.len);
} else {
ret = rdata->rx.len;
} }
return (ret);
}
static unsigned int static unsigned int
xgbe_rx_buf2_len(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata, xgbe_rx_buf2_len(struct xgbe_prv_data *pdata, struct xgbe_ring_data *rdata,
struct xgbe_packet_data *packet, unsigned int len) struct xgbe_packet_data *packet, unsigned int len)
{ {
/* Always the full buffer if not the last descriptor */ /* Always the full buffer if not the last descriptor */
if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) { if (!XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, LAST)) {
axgbe_printf(1, "%s: Not last %d\n", __func__, pdata->rx_buf_size); axgbe_printf(1, "%s: Not last %d\n", __func__, pdata->rx_buf_size);
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesread_again:
context = XGMAC_GET_BITS(packet->attributes, context = XGMAC_GET_BITS(packet->attributes,
RX_PACKET_ATTRIBUTES, CONTEXT); RX_PACKET_ATTRIBUTES, CONTEXT);
if (!context) { if (!context) {
/* Get the data length in the descriptor buffers */ /* Get the data length in the descriptor buffers */
buf1_len = xgbe_rx_buf1_len(pdata, rdata, packet); buf1_len = xgbe_rx_buf1_len(pdata, rdata, packet);
len += buf1_len; len += buf1_len;
if (pdata->sph_enable) {
buf2_len = xgbe_rx_buf2_len(pdata, rdata, packet, len); buf2_len = xgbe_rx_buf2_len(pdata, rdata, packet, len);
len += buf2_len; len += buf2_len;
}
} else } else
buf1_len = buf2_len = 0; buf1_len = buf2_len = 0;
if (packet->errors) if (packet->errors)
axgbe_printf(1, "%s: last %d context %d con_next %d buf1 %d " axgbe_printf(1, "%s: last %d context %d con_next %d buf1 %d "
vmaffioneUnsubmitted
Done
Inline Actions

We could avoid code duplication by executing line 760-761 inconditionally, and lines 762-763 if !sph_enable.

vmaffione: We could avoid code duplication by executing line 760-761 inconditionally, and lines 762-763 if…
"buf2 %d len %d frags %d error %d\n", __func__, last, context, "buf2 %d len %d frags %d error %d\n", __func__, last, context,
context_next, buf1_len, buf2_len, len, i, packet->errors); context_next, buf1_len, buf2_len, len, i, packet->errors);
axgbe_add_frag(pdata, ri, prev_cur, buf1_len, i, 0); axgbe_add_frag(pdata, ri, prev_cur, buf1_len, i, 0);
i++; i++;
if (pdata->sph_enable) {
axgbe_add_frag(pdata, ri, prev_cur, buf2_len, i, 1); axgbe_add_frag(pdata, ri, prev_cur, buf2_len, i, 1);
i++; i++;
}
if (!last || context_next) if (!last || context_next)
goto read_again; goto read_again;
break; break;
vmaffioneUnsubmitted
Done
Inline Actions

same as above

vmaffione: same as above
} }
if (XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CSUM_DONE)) { if (XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CSUM_DONE)) {
ri->iri_csum_flags |= CSUM_IP_CHECKED; ri->iri_csum_flags |= CSUM_IP_CHECKED;
ri->iri_csum_flags |= CSUM_IP_VALID; ri->iri_csum_flags |= CSUM_IP_VALID;
axgbe_printf(2, "%s: csum flags 0x%x\n", __func__, ri->iri_csum_flags); axgbe_printf(2, "%s: csum flags 0x%x\n", __func__, ri->iri_csum_flags);
} }
Show All 11 Lines if (XGMAC_GET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, RSS_HASH)) {
ri->iri_flowid = packet->rss_hash; ri->iri_flowid = packet->rss_hash;
ri->iri_rsstype = packet->rss_hash_type; ri->iri_rsstype = packet->rss_hash_type;
axgbe_printf(2, "%s: hash 0x%x/0x%x rsstype 0x%x/0x%x\n", axgbe_printf(2, "%s: hash 0x%x/0x%x rsstype 0x%x/0x%x\n",
__func__, packet->rss_hash, ri->iri_flowid, __func__, packet->rss_hash, ri->iri_flowid,
packet->rss_hash_type, ri->iri_rsstype); packet->rss_hash_type, ri->iri_rsstype);
} }
if (__predict_false(len == 0)) if (__predict_false(len == 0))
axgbe_error("%s: Zero len packet\n", __func__); axgbe_printf(1, "%s: Discarding Zero len packet\n", __func__);
if (__predict_false(len > max_len)) if (__predict_false(len > max_len))
axgbe_error("%s: Big packet %d/%d\n", __func__, len, max_len); axgbe_error("%s: Big packet %d/%d\n", __func__, len, max_len);
if (__predict_false(packet->errors)) if (__predict_false(packet->errors))
axgbe_printf(1, "<-- %s: rxq: %d len: %d frags: %d cidx %d cur: %d " axgbe_printf(1, "<-- %s: rxq: %d len: %d frags: %d cidx %d cur: %d "
"dirty: %d error 0x%x\n", __func__, ri->iri_qsidx, len, i, "dirty: %d error 0x%x\n", __func__, ri->iri_qsidx, len, i,
ri->iri_cidx, ring->cur, ring->dirty, packet->errors); ri->iri_cidx, ring->cur, ring->dirty, packet->errors);
axgbe_printf(1, "%s: Packet len %d frags %d\n", __func__, len, i); axgbe_printf(1, "%s: Packet len %d frags %d\n", __func__, len, i);
ri->iri_len = len; ri->iri_len = len;
ri->iri_nfrags = i; ri->iri_nfrags = i;
return (0); return (0);
} }