Differential D27970 Diff 81664 usr.sbin/bhyve/pci_emul.c

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usr.sbin/bhyve/pci_emul.c

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	#define CONF1_DATA_PORT 0x0cfc			#define CONF1_DATA_PORT 0x0cfc

	#define CONF1_ENABLE 0x80000000ul			#define CONF1_ENABLE 0x80000000ul

	#define MAXBUSES (PCI_BUSMAX + 1)			#define MAXBUSES (PCI_BUSMAX + 1)
	#define MAXSLOTS (PCI_SLOTMAX + 1)			#define MAXSLOTS (PCI_SLOTMAX + 1)
	#define MAXFUNCS (PCI_FUNCMAX + 1)			#define MAXFUNCS (PCI_FUNCMAX + 1)

				#define GB (1024 * 1024 * 1024UL)

	struct funcinfo {			struct funcinfo {
	char *fi_name;			char *fi_name;
	char *fi_param;			char *fi_param;
	struct pci_devinst *fi_devi;			struct pci_devinst *fi_devi;
	};			};

	struct intxinfo {			struct intxinfo {
	int ii_count;			int ii_count;
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	#define PCI_EMUL_IOBASE 0x2000			#define PCI_EMUL_IOBASE 0x2000
	#define PCI_EMUL_IOLIMIT 0x10000			#define PCI_EMUL_IOLIMIT 0x10000

	#define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */			#define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
	#define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */			#define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
	SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);			SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);

	#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE			#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
				#define PCI_EMUL_MEMSIZE64 (32*GB)

	static struct pci_devemu pci_emul_finddev(char name);			static struct pci_devemu pci_emul_finddev(char name);
	static void pci_lintr_route(struct pci_devinst *pi);			static void pci_lintr_route(struct pci_devinst *pi);
	static void pci_lintr_update(struct pci_devinst *pi);			static void pci_lintr_update(struct pci_devinst *pi);
	static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,			static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
	int func, int coff, int bytes, uint32_t *val);			int func, int coff, int bytes, uint32_t *val);

	static __inline void			static __inline void
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	{			{

	return (PCI_EMUL_ECFG_BASE);			return (PCI_EMUL_ECFG_BASE);
	}			}

	#define BUSIO_ROUNDUP 32			#define BUSIO_ROUNDUP 32
	#define BUSMEM_ROUNDUP (1024 * 1024)			#define BUSMEM_ROUNDUP (1024 * 1024)

				#define ALIGN_VALUE(Value, Alignment) ((Value) + (((Alignment) - (Value)) & ((Alignment) - 1)))

	int			int
	init_pci(struct vmctx *ctx)			init_pci(struct vmctx *ctx)
	{			{
	struct mem_range mr;			struct mem_range mr;
	struct pci_devemu *pde;			struct pci_devemu *pde;
	struct businfo *bi;			struct businfo *bi;
	struct slotinfo *si;			struct slotinfo *si;
	struct funcinfo *fi;			struct funcinfo *fi;
	size_t lowmem;			size_t lowmem;
	uint64_t cpu_maxphysaddr, pci_emul_memresv64;
	u_int regs[4];
	int bus, slot, func, error;			int bus, slot, func, error;

	pci_emul_iobase = PCI_EMUL_IOBASE;			pci_emul_iobase = PCI_EMUL_IOBASE;
	pci_emul_membase32 = vm_get_lowmem_limit(ctx);			pci_emul_membase32 = vm_get_lowmem_limit(ctx);

	do_cpuid(0x80000008, regs);			pci_emul_membase64 = 4*GB + vm_get_highmem_size(ctx);
	cpu_maxphysaddr = 1ULL << (regs[0] & 0xff);			pci_emul_membase64 = ALIGN_VALUE(pci_emul_membase64, PCI_EMUL_MEMSIZE64);
	if (cpu_maxphysaddr > VM_MAXUSER_ADDRESS)			pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64;
	cpu_maxphysaddr = VM_MAXUSER_ADDRESS;
	pci_emul_memresv64 = cpu_maxphysaddr / 4;
	/*
	* Max power of 2 that is less then
	* cpu_maxphysaddr - pci_emul_memresv64.
	*/
	pci_emul_membase64 = 1ULL << (flsl(cpu_maxphysaddr -
	pci_emul_memresv64) - 1);
	pci_emul_memlim64 = cpu_maxphysaddr;

	for (bus = 0; bus < MAXBUSES; bus++) {			for (bus = 0; bus < MAXBUSES; bus++) {
	if ((bi = pci_businfo[bus]) == NULL)			if ((bi = pci_businfo[bus]) == NULL)
	continue;			continue;
	/*			/*
	* Keep track of the i/o and memory resources allocated to			* Keep track of the i/o and memory resources allocated to
	* this bus.			* this bus.
	*/			*/
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