Changeset View
Changeset View
Standalone View
Standalone View
sys/dev/hwpmc/hwpmc_armv7.c
| Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines | armv7_counter_disable(unsigned int pmc) | ||||
| reg = (1 << pmc); | reg = (1 << pmc); | ||||
| cp15_pmcnten_clr(reg); | cp15_pmcnten_clr(reg); | ||||
| } | } | ||||
| /* | /* | ||||
| * Performance Count Register N | * Performance Count Register N | ||||
| */ | */ | ||||
| static uint32_t | static uint32_t | ||||
| armv7_pmcn_read(unsigned int pmc) | armv7_pmcn_read(unsigned int pmc, uint32_t evsel) | ||||
| { | { | ||||
| if (evsel == PMC_EV_CPU_CYCLES) { | |||||
| return ((uint32_t)cp15_pmccntr_get()); | |||||
| } | |||||
| KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); | KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); | ||||
| cp15_pmselr_set(pmc); | cp15_pmselr_set(pmc); | ||||
| return (cp15_pmxevcntr_get()); | return (cp15_pmxevcntr_get()); | ||||
| } | } | ||||
| static uint32_t | static uint32_t | ||||
| armv7_pmcn_write(unsigned int pmc, uint32_t reg) | armv7_pmcn_write(unsigned int pmc, uint32_t reg) | ||||
| Show All 37 Lines | |||||
| } | } | ||||
| static int | static int | ||||
| armv7_read_pmc(int cpu, int ri, pmc_value_t *v) | armv7_read_pmc(int cpu, int ri, pmc_value_t *v) | ||||
| { | { | ||||
| pmc_value_t tmp; | pmc_value_t tmp; | ||||
| struct pmc *pm; | struct pmc *pm; | ||||
| register_t s; | |||||
| u_int reg; | |||||
| KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), | KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), | ||||
| ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); | ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); | ||||
| KASSERT(ri >= 0 && ri < armv7_npmcs, | KASSERT(ri >= 0 && ri < armv7_npmcs, | ||||
| ("[armv7,%d] illegal row index %d", __LINE__, ri)); | ("[armv7,%d] illegal row index %d", __LINE__, ri)); | ||||
| pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; | pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; | ||||
| s = intr_disable(); | |||||
| tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); | |||||
| /* Check if counter has overflowed */ | |||||
| if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) | if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) | ||||
| tmp = (uint32_t)cp15_pmccntr_get(); | reg = (1u << 31); | ||||
| else | else | ||||
| tmp = armv7_pmcn_read(ri); | reg = (1u << ri); | ||||
| if ((cp15_pmovsr_get() & reg) != 0) { | |||||
| /* Clear Overflow Flag */ | |||||
| cp15_pmovsr_set(reg); | |||||
| if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) | |||||
| pm->pm_overflowcnt += 1; | |||||
| /* Reread counter in case we raced. */ | |||||
| tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); | |||||
| } | |||||
| tmp += 0x100000000llu * pm->pm_overflowcnt; | tmp += 0x100000000llu * pm->pm_overflowcnt; | ||||
| intr_restore(s); | |||||
| PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); | PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); | ||||
| if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) | if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) | ||||
| *v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); | *v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); | ||||
| else | else | ||||
| *v = tmp; | *v = tmp; | ||||
| return 0; | return 0; | ||||
| ▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines | armv7_intr(struct trapframe *tf) | ||||
| for (ri = 0; ri < armv7_npmcs; ri++) { | for (ri = 0; ri < armv7_npmcs; ri++) { | ||||
| pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; | pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; | ||||
| if (pm == NULL) | if (pm == NULL) | ||||
| continue; | continue; | ||||
| /* Check if counter has overflowed */ | /* Check if counter has overflowed */ | ||||
| if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) | if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) | ||||
| reg = (1 << 31); | reg = (1u << 31); | ||||
| else | else | ||||
| reg = (1 << ri); | reg = (1u << ri); | ||||
| if ((cp15_pmovsr_get() & reg) == 0) { | if ((cp15_pmovsr_get() & reg) == 0) { | ||||
| continue; | continue; | ||||
| } | } | ||||
| /* Clear Overflow Flag */ | /* Clear Overflow Flag */ | ||||
| cp15_pmovsr_set(reg); | cp15_pmovsr_set(reg); | ||||
| ▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines | |||||