Differential D27889 Diff 81607 sys/arm/ti/clk/ti_clk_clkctrl.c

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sys/arm/ti/clk/ti_clk_clkctrl.c

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#include <sys/malloc.h>		#include <sys/malloc.h>

#include <dev/extres/clk/clk.h>		#include <dev/extres/clk/clk.h>

#include <arm/ti/clk/ti_clk_clkctrl.h>		#include <arm/ti/clk/ti_clk_clkctrl.h>

#include "clkdev_if.h"		#include "clkdev_if.h"

#if 0		#if 1
#define DPRINTF(dev, msg...) device_printf(dev, msg)		#define DPRINTF(dev, msg...) device_printf(dev, msg)
#else		#else
#define DPRINTF(dev, msg...)		#define DPRINTF(dev, msg...)
#endif		#endif

/*		/*
* clknode for clkctrl, implements gate and mux (for gpioc)		* clknode for clkctrl, implements gate and mux (for gpioc)
*/		*/
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ti_clkctrl_set_gdbclk_gate(struct clknode *clk, bool enable)		ti_clkctrl_set_gdbclk_gate(struct clknode *clk, bool enable)
{		{
struct ti_clkctrl_clknode_sc *sc;		struct ti_clkctrl_clknode_sc *sc;
uint32_t val, gpio_x_gdbclk;		uint32_t val, gpio_x_gdbclk;
uint32_t timeout = 100;		uint32_t timeout = 100;

sc = clknode_get_softc(clk);		sc = clknode_get_softc(clk);

		DEVICE_LOCK(clk);
READ4(clk, sc->register_offset, &val);		READ4(clk, sc->register_offset, &val);
DPRINTF(sc->dev, "val(%x) & (%x \| %x = %x)\n",		DPRINTF(sc->dev, "val(%x) & (%x \| %x = %x)\n",
val, GPIO_X_GDBCLK_MASK, MODULEMODE_MASK,		val, GPIO_X_GDBCLK_MASK, MODULEMODE_MASK,
GPIO_X_GDBCLK_MASK \| MODULEMODE_MASK);		GPIO_X_GDBCLK_MASK \| MODULEMODE_MASK);

if (enable) {		if (enable) {
val = val & MODULEMODE_MASK;		val = val & MODULEMODE_MASK;
val \|= GPIOX_GDBCLK_ENABLE;		val \|= GPIOX_GDBCLK_ENABLE;
Show All 11 Lines	while (timeout) {
gpio_x_gdbclk = val & GPIO_X_GDBCLK_MASK;		gpio_x_gdbclk = val & GPIO_X_GDBCLK_MASK;
if (enable && (gpio_x_gdbclk == GPIOX_GDBCLK_ENABLE))		if (enable && (gpio_x_gdbclk == GPIOX_GDBCLK_ENABLE))
break;		break;
else if (!enable && (gpio_x_gdbclk == GPIOX_GDBCLK_DISABLE))		else if (!enable && (gpio_x_gdbclk == GPIOX_GDBCLK_DISABLE))
break;		break;
DELAY(10);		DELAY(10);
timeout--;		timeout--;
}		}
		DEVICE_UNLOCK(clk);

if (timeout == 0) {		if (timeout == 0) {
device_printf(sc->dev, "ti_clkctrl_set_gdbclk_gate: Timeout\n");		device_printf(sc->dev, "ti_clkctrl_set_gdbclk_gate: Timeout\n");
return (1);		return (1);
}		}

return (0);		return (0);
}		}

static int		static int
ti_clkctrl_set_gate(struct clknode *clk, bool enable)		ti_clkctrl_set_gate(struct clknode *clk, bool enable)
{		{
struct ti_clkctrl_clknode_sc *sc;		struct ti_clkctrl_clknode_sc *sc;
uint32_t val, idlest, module;		uint32_t val, idlest, module;
uint32_t timeout=100;		uint32_t timeout=100;
int err;		int err;

sc = clknode_get_softc(clk);		sc = clknode_get_softc(clk);

if (sc->gdbclk) {		if (sc->gdbclk) {
err = ti_clkctrl_set_gdbclk_gate(clk, enable);		err = ti_clkctrl_set_gdbclk_gate(clk, enable);
return (err);		return (err);
}		}
		DEVICE_LOCK(clk);
READ4(clk, sc->register_offset, &val);		READ4(clk, sc->register_offset, &val);

if (enable)		if (enable)
WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);		WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);
else		else
WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);		WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);

while (timeout) {		while (timeout) {
READ4(clk, sc->register_offset, &val);		READ4(clk, sc->register_offset, &val);
idlest = val & IDLEST_MASK;		idlest = val & IDLEST_MASK;
module = val & MODULEMODE_MASK;		module = val & MODULEMODE_MASK;
if (enable &&		if (enable &&
(idlest == IDLEST_FUNC \|\| idlest == IDLEST_TRANS) &&		(idlest == IDLEST_FUNC \|\| idlest == IDLEST_TRANS) &&
module == MODULEMODE_ENABLE)		module == MODULEMODE_ENABLE)
break;		break;
else if (!enable &&		else if (!enable &&
idlest == IDLEST_DISABLE &&		idlest == IDLEST_DISABLE &&
module == MODULEMODE_DISABLE)		module == MODULEMODE_DISABLE)
break;		break;
DELAY(10);		DELAY(10);
timeout--;		timeout--;
}		}

		DEVICE_UNLOCK(clk);
if (timeout == 0) {		if (timeout == 0) {
device_printf(sc->dev, "ti_clkctrl_set_gate: Timeout\n");		device_printf(sc->dev, "ti_clkctrl_set_gate: Timeout\n");
return (1);		return (1);
}		}

return (0);		return (0);
}		}

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