Differential D27889 Diff 81498 sys/arm/ti/clk/ti_mux_clock.c

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sys/arm/ti/clk/ti_mux_clock.c

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#include <sys/libkern.h>		#include <sys/libkern.h>
#include <sys/types.h>		#include <sys/types.h>
#include <sys/malloc.h>		#include <sys/malloc.h>

#include <machine/bus.h>		#include <machine/bus.h>
#include <dev/fdt/simplebus.h>		#include <dev/fdt/simplebus.h>

#include <dev/extres/clk/clk_mux.h>		#include <dev/extres/clk/clk_mux.h>
		#include <dev/extres/syscon/syscon.h>

#include <dev/ofw/ofw_bus.h>		#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>		#include <dev/ofw/ofw_bus_subr.h>

#include "clock_common.h"		#include "clock_common.h"
		#include "clkdev_if.h"
		#include "syscon_if.h"

#if 0		#if 1
#define DPRINTF(dev, msg...) device_printf(dev, msg)		#define DPRINTF(dev, msg...) device_printf(dev, msg)
#else		#else
#define DPRINTF(dev, msg...)		#define DPRINTF(dev, msg...)
#endif		#endif


		PLIST(sys_clkin_ck_parent) = { "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck", "virt_26000000_ck" };
		PLIST(pruss_ocp_gclk_parent) = { "l3_gclk", "dpll_disp_m2_ck@4a4" };
		PLIST(timer1_fck_parent) = { "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0", "tclkin_ck", "clk_rc32k_ck", "clk_32768_ck" };
		PLIST(timer2_fck_parent) = { "tclkin_ck", "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0" };
		PLIST(timer3_fck_parent) = { "tclkin_ck", "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0" };
		PLIST(timer4_fck_parent) = { "tclkin_ck", "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0" };
		PLIST(timer5_fck_parent) = { "tclkin_ck", "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0" };
		PLIST(timer6_fck_parent) = { "tclkin_ck", "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0" };
		PLIST(timer7_fck_parent) = { "tclkin_ck", "sys_clkin_ck@40", "clk-24mhz-clkctrl@14c_0" };
		PLIST(wdt1_fck_parent) = { "clk_rc32k_ck", "clk-24mhz-clkctrl@14c_0" };
		PLIST(cpsw_cpts_tft_clk_parent) = { "dpll_core_m5_ck@484", "dpll_core_m4_ck@480" };
		PLIST(gpio0_dbclk_mux_ck_parent) = { "clk_rc32k_ck", "clk_32768_ck", "clk-24mhz-clkctrl@14c_0" };
		PLIST(lcd_gclk_parent) = { "dpll_disp_m2_ck@4a4", "dpll_core_m5_ck@484", "dpll_per_m2_ck@4ac" };
		PLIST(gfx_fclk_clksel_ck_parent) = { "dpll_core_m4_ck@480", "dpll_per_m2_ck@4ac" };
		PLIST(sysclkout_pre_ck_parent) = { "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck@4a0", "dpll_per_m2_ck@4ac", "lcd_gclk@534" };

		static struct parent_lookup_table mux_parent_table[] = {
		{ "sys_clkin_ck@40", nitems(sys_clkin_ck_parent), sys_clkin_ck_parent },
		{ "pruss_ocp_gclk@530", nitems(pruss_ocp_gclk_parent), pruss_ocp_gclk_parent },
		{ "timer1_fck@528", nitems(timer1_fck_parent), timer1_fck_parent },
		{ "timer2_fck@508", nitems(timer2_fck_parent), timer2_fck_parent },
		{ "timer3_fck@50c", nitems(timer3_fck_parent), timer3_fck_parent },
		{ "timer4_fck@510", nitems(timer4_fck_parent), timer4_fck_parent },
		{ "timer5_fck@518", nitems(timer5_fck_parent), timer5_fck_parent },
		{ "timer6_fck@51c", nitems(timer6_fck_parent), timer6_fck_parent },
		{ "timer7_fck@504", nitems(timer7_fck_parent), timer7_fck_parent },
		{ "wdt1_fck@538", nitems(wdt1_fck_parent), wdt1_fck_parent },
		{ "cpsw_cpts_rft_clk@520", nitems(cpsw_cpts_tft_clk_parent), cpsw_cpts_tft_clk_parent },
		{ "gpio0_dbclk_mux_ck@53c", nitems(gpio0_dbclk_mux_ck_parent), gpio0_dbclk_mux_ck_parent },
		{ "lcd_gclk@534", nitems(lcd_gclk_parent), lcd_gclk_parent },
		{ "gfx_fclk_clksel_ck@52c", nitems(gfx_fclk_clksel_ck_parent), gfx_fclk_clksel_ck_parent },
		{ "sysclkout_pre_ck@700", nitems(sysclkout_pre_ck_parent), sysclkout_pre_ck_parent },
		};

/*		/*
* Devicetree description		* Devicetree description
* Documentation/devicetree/bindings/clock/ti/mux.txt		* Documentation/devicetree/bindings/clock/ti/mux.txt
*/		*/

struct ti_mux_softc {		struct ti_mux_softc {
device_t sc_dev;		device_t sc_dev;
bool attach_done;

struct clk_mux_def mux_def;		struct clk_mux_def mux_def;
struct clock_cell_info clock_cell;
struct clkdom *clkdom;		struct clkdom *clkdom;
		struct syscon *syscon;
};		};

static int ti_mux_probe(device_t dev);		static int ti_mux_probe(device_t dev);
static int ti_mux_attach(device_t dev);		static int ti_mux_attach(device_t dev);
static int ti_mux_detach(device_t dev);		static int ti_mux_detach(device_t dev);

#define TI_MUX_CLOCK 2		#define TI_MUX_CLOCK 2
#define TI_COMPOSITE_MUX_CLOCK 1		#define TI_COMPOSITE_MUX_CLOCK 1
#define TI_MUX_END 0		#define TI_MUX_END 0

static struct ofw_compat_data compat_data[] = {		static struct ofw_compat_data compat_data[] = {
{ "ti,mux-clock", TI_MUX_CLOCK },		{ "ti,mux-clock", TI_MUX_CLOCK },
{ "ti,composite-mux-clock", TI_COMPOSITE_MUX_CLOCK },		{ "ti,composite-mux-clock", TI_COMPOSITE_MUX_CLOCK },
{ NULL, TI_MUX_END }		{ NULL, TI_MUX_END }
};		};

static int		static int
		ti_mux_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val)
		{
		struct ti_mux_softc *sc;

		sc = device_get_softc(dev);
		DPRINTF(sc->sc_dev, "mux_clkdev_write_4: addr %x val %x\n", addr, val);
		return (SYSCON_UNLOCKED_WRITE_4(sc->syscon, addr, val));
		}

		static int
		ti_mux_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
		{
		struct ti_mux_softc *sc;
		uint32_t rdval;

		sc = device_get_softc(dev);

		rdval = SYSCON_UNLOCKED_READ_4(sc->syscon, addr);
		*val = rdval;
		DPRINTF(sc->sc_dev, "clkdev_read_4: addr %x val %x\n", addr, *val);
		return (0);
		}

		static int
		ti_mux_clkdev_modify_4(device_t dev, bus_addr_t addr,
		uint32_t clear_mask, uint32_t set_mask)
		{
		struct ti_mux_softc *sc;

		sc = device_get_softc(dev);
		DPRINTF(sc->sc_dev, "clkdev_modify_4: addr %x clear %x mask %x\n", addr, clear_mask, set_mask);
		return (SYSCON_UNLOCKED_MODIFY_4(sc->syscon, addr, clear_mask,
		set_mask));
		}

		static void
		ti_mux_clkdev_device_lock(device_t dev)
		{
		struct ti_mux_softc *sc;

		sc = device_get_softc(dev);
		DPRINTF(sc->sc_dev, "ti_mux_clkdev_device_lock\n");
		SYSCON_DEVICE_LOCK(sc->syscon->pdev);
		}

		static void
		ti_mux_clkdev_device_unlock(device_t dev)
		{
		struct ti_mux_softc *sc;

		sc = device_get_softc(dev);
		DPRINTF(sc->sc_dev, "ti_mux_clkdev_device_unlock\n");
		SYSCON_DEVICE_UNLOCK(sc->syscon->pdev);
		}


		static int
ti_mux_probe(device_t dev)		ti_mux_probe(device_t dev)
{		{
if (!ofw_bus_status_okay(dev))		if (!ofw_bus_status_okay(dev))
return (ENXIO);		return (ENXIO);

if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)		if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);		return (ENXIO);

Show All 26 Lines	register_clk(struct ti_mux_softc *sc) {

return 0;		return 0;
}		}

static int		static int
ti_mux_attach(device_t dev)		ti_mux_attach(device_t dev)
{		{
struct ti_mux_softc *sc;		struct ti_mux_softc *sc;
phandle_t node;		phandle_t node;
int err;		int err, index;
cell_t value;		cell_t value;
		const char *node_name;

sc = device_get_softc(dev);		sc = device_get_softc(dev);
sc->sc_dev = dev;		sc->sc_dev = dev;
node = ofw_bus_get_node(dev);		node = ofw_bus_get_node(dev);

		err = SYSCON_GET_HANDLE(device_get_parent(dev), &sc->syscon);
		if (err != 0) {
		panic("Cannot get syscon handle.\n");
		}

		node_name = ofw_bus_get_name(dev);
		if (node_name == NULL) {
		panic("Cannot get name of the clock node");
		}

/* Grab the content of reg properties */		/* Grab the content of reg properties */
OF_getencprop(node, "reg", &value, sizeof(value));		OF_getencprop(node, "reg", &value, sizeof(value));
sc->mux_def.offset = value;		sc->mux_def.offset = value;

if (OF_hasprop(node, "ti,bit-shift")) {		if (OF_hasprop(node, "ti,bit-shift")) {
OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));		OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));
sc->mux_def.shift = value;		sc->mux_def.shift = value;
DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->mux_def.shift);		DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->mux_def.shift);
}		}
if (OF_hasprop(node, "ti,index-starts-at-one")) {		if (OF_hasprop(node, "ti,index-starts-at-one")) {
/* FIXME: Add support in dev/extres/clk */		/* FIXME: Add support in dev/extres/clk */
/sc->mux_def.mux_flags = ... /		/sc->mux_def.mux_flags = ... /
device_printf(sc->sc_dev, "ti,index-starts-at-one - Not implemented\n");		device_printf(sc->sc_dev, "ti,index-starts-at-one - Not implemented\n");
}		}

if (OF_hasprop(node, "ti,set-rate-parent"))		if (OF_hasprop(node, "ti,set-rate-parent"))
device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n");		device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n");
if (OF_hasprop(node, "ti,latch-bit"))		if (OF_hasprop(node, "ti,latch-bit"))
device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n");		device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n");

read_clock_cells(sc->sc_dev, &sc->clock_cell);		/* Fill clknode_init_def */
		((struct clknode_init_def *)&sc->mux_def.clkdef)->id = 1;
		((struct clknode_init_def *)&sc->mux_def.clkdef)->flags = CLK_NODE_STATIC_STRINGS;

create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->mux_def.clkdef);		/* Find parent in lookup table */
		for (index = 0; index < nitems(mux_parent_table); index++) {
		if (strcmp(node_name, mux_parent_table[index].node_name) == 0) {
		device_printf(dev, "!!! Found %s in lookup table index %d\n",
		node_name, index);


		((struct clknode_init_def *)&sc->mux_def.clkdef)->name = mux_parent_table[index].node_name;
		((struct clknode_init_def *)&sc->mux_def.clkdef)->parent_cnt = mux_parent_table[index].parent_cnt;
		((struct clknode_init_def *)&sc->mux_def.clkdef)->parent_names = mux_parent_table[index].parent_names;
		break;
		}
		}
		if (index == nitems(mux_parent_table))
		panic("Cant find clock %s\n", sc->mux_def.clkdef.name);

/* Figure out the width from ti_max_div */		/* Figure out the width from ti_max_div */
if (sc->mux_def.mux_flags)		if (sc->mux_def.mux_flags)
sc->mux_def.width = fls(sc->clock_cell.num_real_clocks-1);		sc->mux_def.width = fls(((struct clknode_init_def *)&sc->mux_def.clkdef)->parent_cnt-1);
else		else
sc->mux_def.width = fls(sc->clock_cell.num_real_clocks);		sc->mux_def.width = fls(((struct clknode_init_def *)&sc->mux_def.clkdef)->parent_cnt);

DPRINTF(sc->sc_dev, "sc->clock_cell.num_real_clocks %x def.width %x\n",		DPRINTF(sc->sc_dev, "parents %x def.width %x\n",
sc->clock_cell.num_real_clocks, sc->mux_def.width);		((struct clknode_init_def *)&sc->mux_def.clkdef)->parent_cnt, sc->mux_def.width);

err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->mux_def.clkdef);

if (err) {
/* free_clkdef will be called in ti_mux_new_pass */
DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");
return (bus_generic_attach(sc->sc_dev));
}

err = register_clk(sc);		err = register_clk(sc);

if (err) {		if (err != 0) {
/* free_clkdef will be called in ti_mux_new_pass */		DPRINTF(sc->sc_dev, "Cannot register clock\n");
DPRINTF(sc->sc_dev, "register_clk failed\n");		return (ENXIO);
return (bus_generic_attach(sc->sc_dev));
}		}

sc->attach_done = true;

free_clkdef(&sc->mux_def.clkdef);

return (bus_generic_attach(sc->sc_dev));		return (bus_generic_attach(sc->sc_dev));
}		}

static void
ti_mux_new_pass(device_t dev)
{
struct ti_mux_softc *sc;
int err;

sc = device_get_softc(dev);

if (sc->attach_done) {
return;
}

err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->mux_def.clkdef);
if (err) {
/* free_clkdef will be called in later call to ti_mux_new_pass */
DPRINTF(sc->sc_dev, "ti_mux_new_pass find_parent_clock_names failed\n");
return;
}

err = register_clk(sc);
if (err) {
/* free_clkdef will be called in later call to ti_mux_new_pass */
DPRINTF(sc->sc_dev, "ti_mux_new_pass register_clk failed\n");
return;
}

sc->attach_done = true;

free_clkdef(&sc->mux_def.clkdef);
}

static int		static int
ti_mux_detach(device_t dev)		ti_mux_detach(device_t dev)
{		{
return (EBUSY);		return (EBUSY);
}		}

static device_method_t ti_mux_methods[] = {		static device_method_t ti_mux_methods[] = {
/* Device interface */		/* Device interface */
DEVMETHOD(device_probe, ti_mux_probe),		DEVMETHOD(device_probe, ti_mux_probe),
DEVMETHOD(device_attach, ti_mux_attach),		DEVMETHOD(device_attach, ti_mux_attach),
DEVMETHOD(device_detach, ti_mux_detach),		DEVMETHOD(device_detach, ti_mux_detach),

/* Bus interface */		/* Clock device interface */
DEVMETHOD(bus_new_pass, ti_mux_new_pass),		DEVMETHOD(clkdev_device_lock, ti_mux_clkdev_device_lock),
		DEVMETHOD(clkdev_device_unlock, ti_mux_clkdev_device_unlock),
		DEVMETHOD(clkdev_read_4, ti_mux_clkdev_read_4),
		DEVMETHOD(clkdev_write_4, ti_mux_clkdev_write_4),
		DEVMETHOD(clkdev_modify_4, ti_mux_clkdev_modify_4),

DEVMETHOD_END		DEVMETHOD_END
};		};

DEFINE_CLASS_0(ti_mux, ti_mux_driver, ti_mux_methods,		DEFINE_CLASS_0(ti_mux, ti_mux_driver, ti_mux_methods,
sizeof(struct ti_mux_softc));		sizeof(struct ti_mux_softc));

static devclass_t ti_mux_devclass;		static devclass_t ti_mux_devclass;

EARLY_DRIVER_MODULE(ti_mux, simplebus, ti_mux_driver,		EARLY_DRIVER_MODULE(ti_mux, simplebus, ti_mux_driver,
ti_mux_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);		ti_mux_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
MODULE_VERSION(ti_mux, 1);		MODULE_VERSION(ti_mux, 1);