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sys/arm/include/armreg.h
Show First 20 Lines • Show All 438 Lines • ▼ Show 20 Lines | |||||
* |c c c c| | | * |c c c c| | | ||||
* +-------+-------------------------------------------------------+ | * +-------+-------------------------------------------------------+ | ||||
*/ | */ | ||||
#define INSN_SIZE 4 /* Always 4 bytes */ | #define INSN_SIZE 4 /* Always 4 bytes */ | ||||
#define INSN_COND_MASK 0xf0000000 /* Condition mask */ | #define INSN_COND_MASK 0xf0000000 /* Condition mask */ | ||||
#define INSN_COND_AL 0xe0000000 /* Always condition */ | #define INSN_COND_AL 0xe0000000 /* Always condition */ | ||||
/* ARM register defines */ | |||||
#define ARM_REG_SIZE 4 | |||||
#define ARM_REG_NUM_PC 15 | |||||
#define ARM_REG_NUM_LR 14 | |||||
#define ARM_REG_NUM_SP 13 | |||||
/* ARM constants for 32-bit instruction opcode matching (for debug only) */ | |||||
#define DB_ARM_INST_BRANCH_MASK 0x0E000000 | |||||
#define DB_ARM_INST_BRANCH_MATCH 0x0A000000 | |||||
#define DB_ARM_INST_BRANCH_OFF_MASK 0x00FFFFFF | |||||
#define DB_ARM_INST_BRANCH_PC_AHEAD 8 | |||||
#define DB_ARM_INST_BRANCHX_MASK 0x0FFFFFD0 | |||||
#define DB_ARM_INST_BRANCHX_MATCH 0x012FFF10 | |||||
#define DB_ARM_INST_BRANCHX_REG_MASK 0xF | |||||
#define DB_ARM_INST_LDR_PC_MASK 0x0C00F000 | |||||
#define DB_ARM_INST_LDR_PC_MATCH 0x0400F000 | |||||
#define DB_ARM_INST_LDR_PC_IOREG_OFF_FLAG (1 << 25) | |||||
#define DB_ARM_INST_LDR_PC_IOREG_MASK 0xF | |||||
#define DB_ARM_INST_LDR_PC_SHIFT_OFF 4 | |||||
#define DB_ARM_INST_LDR_PC_SHIFT_MASK 0xFF | |||||
#define DB_ARM_INST_LDR_PC_IMM_MASK 0xFFF | |||||
#define DB_ARM_INST_LDR_PC_REG_UP_FLAG (1 << 23) | |||||
#define DB_ARM_INST_LDR_PC_BASEREG_OFF (16) | |||||
#define DB_ARM_INST_LDR_PC_BASEREG_MASK 0xF | |||||
#define DB_ARM_INST_POP_PC_MASK 0x0E108000 | |||||
#define DB_ARM_INST_POP_PC_MATCH 0x08108000 | |||||
#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ | #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ | ||||
#endif /* !MACHINE_ARMREG_H */ | #endif /* !MACHINE_ARMREG_H */ |