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head/sys/dev/ichiic/ig4_pci.c
| Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines | |||||
| #define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086 | #define PCI_CHIP_COMETLAKE_H_I2C_0 0x06e88086 | ||||
| #define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086 | #define PCI_CHIP_COMETLAKE_H_I2C_1 0x06e98086 | ||||
| #define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086 | #define PCI_CHIP_COMETLAKE_H_I2C_2 0x06ea8086 | ||||
| #define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086 | #define PCI_CHIP_COMETLAKE_H_I2C_3 0x06eb8086 | ||||
| #define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086 | #define PCI_CHIP_COMETLAKE_V_I2C_0 0xa3e08086 | ||||
| #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 | #define PCI_CHIP_COMETLAKE_V_I2C_1 0xa3e18086 | ||||
| #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 | #define PCI_CHIP_COMETLAKE_V_I2C_2 0xa3e28086 | ||||
| #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 | #define PCI_CHIP_COMETLAKE_V_I2C_3 0xa3e38086 | ||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_0 0x43d88086 | |||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_1 0x43e88086 | |||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_2 0x43e98086 | |||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_3 0x43ea8086 | |||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_4 0x43eb8086 | |||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_5 0x43ad8086 | |||||
| #define PCI_CHIP_TIGERLAKE_H_I2C_6 0x43ae8086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_0 0xa0c58086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_1 0xa0c68086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_2 0xa0d88086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_3 0xa0d98086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_4 0xa0e88086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_5 0xa0e98086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_6 0xa0ea8086 | |||||
| #define PCI_CHIP_TIGERLAKE_LP_I2C_7 0xa0eb8086 | |||||
| struct ig4iic_pci_device { | struct ig4iic_pci_device { | ||||
| uint32_t devid; | uint32_t devid; | ||||
| const char *desc; | const char *desc; | ||||
| enum ig4_vers version; | enum ig4_vers version; | ||||
| }; | }; | ||||
| static struct ig4iic_pci_device ig4iic_pci_devices[] = { | static struct ig4iic_pci_device ig4iic_pci_devices[] = { | ||||
| ▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines | static struct ig4iic_pci_device ig4iic_pci_devices[] = { | ||||
| { PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_H_I2C_0, "Intel Comet Lake-H I2C Controller-0", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_H_I2C_1, "Intel Comet Lake-H I2C Controller-1", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_H_I2C_2, "Intel Comet Lake-H I2C Controller-2", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_H_I2C_3, "Intel Comet Lake-H I2C Controller-3", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_V_I2C_0, "Intel Comet Lake-V I2C Controller-0", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_V_I2C_1, "Intel Comet Lake-V I2C Controller-1", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_V_I2C_2, "Intel Comet Lake-V I2C Controller-2", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, | { PCI_CHIP_COMETLAKE_V_I2C_3, "Intel Comet Lake-V I2C Controller-3", IG4_CANNONLAKE}, | ||||
| { PCI_CHIP_TIGERLAKE_H_I2C_0, "Intel Tiger Lake-H I2C Controller-0", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_H_I2C_1, "Intel Tiger Lake-H I2C Controller-1", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_H_I2C_2, "Intel Tiger Lake-H I2C Controller-2", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_H_I2C_3, "Intel Tiger Lake-H I2C Controller-3", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_H_I2C_4, "Intel Tiger Lake-H I2C Controller-4", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_H_I2C_5, "Intel Tiger Lake-H I2C Controller-5", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_H_I2C_6, "Intel Tiger Lake-H I2C Controller-6", IG4_TIGERLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_0, "Intel Tiger Lake-LP I2C Controller-0", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_1, "Intel Tiger Lake-LP I2C Controller-1", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_2, "Intel Tiger Lake-LP I2C Controller-2", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_3, "Intel Tiger Lake-LP I2C Controller-3", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_4, "Intel Tiger Lake-LP I2C Controller-4", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_5, "Intel Tiger Lake-LP I2C Controller-5", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_6, "Intel Tiger Lake-LP I2C Controller-6", IG4_SKYLAKE}, | |||||
| { PCI_CHIP_TIGERLAKE_LP_I2C_7, "Intel Tiger Lake-LP I2C Controller-7", IG4_SKYLAKE}, | |||||
| }; | }; | ||||
| static int | static int | ||||
| ig4iic_pci_probe(device_t dev) | ig4iic_pci_probe(device_t dev) | ||||
| { | { | ||||
| ig4iic_softc_t *sc = device_get_softc(dev); | ig4iic_softc_t *sc = device_get_softc(dev); | ||||
| uint32_t devid; | uint32_t devid; | ||||
| int i; | int i; | ||||
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