Differential D27225 Diff 80108 head/sys/dev/ahci/ahci.h

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head/sys/dev/ahci/ahci.h

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#define AHCI_P_DEVSLP_DETO_SHIFT 2		#define AHCI_P_DEVSLP_DETO_SHIFT 2
#define AHCI_P_DEVSLP_MDAT 0x00007c00		#define AHCI_P_DEVSLP_MDAT 0x00007c00
#define AHCI_P_DEVSLP_MDAT_SHIFT 10		#define AHCI_P_DEVSLP_MDAT_SHIFT 10
#define AHCI_P_DEVSLP_DITO 0x01ff8000		#define AHCI_P_DEVSLP_DITO 0x01ff8000
#define AHCI_P_DEVSLP_DITO_SHIFT 15		#define AHCI_P_DEVSLP_DITO_SHIFT 15
#define AHCI_P_DEVSLP_DM 0x0e000000		#define AHCI_P_DEVSLP_DM 0x0e000000
#define AHCI_P_DEVSLP_DM_SHIFT 25		#define AHCI_P_DEVSLP_DM_SHIFT 25

/* Just to be sure, if building as module. */
#if MAXPHYS < 512 * 1024
#undef MAXPHYS
#define MAXPHYS 512 * 1024
#endif
/* Pessimistic prognosis on number of required S/G entries */		/* Pessimistic prognosis on number of required S/G entries */
#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))		#define AHCI_SG_ENTRIES MIN(roundup(btoc(maxphys) + 1, 8), 65528)
/* Command list. 32 commands. First, 1Kbyte aligned. */		/* Command list. 32 commands. First, 1Kbyte aligned. */
#define AHCI_CL_OFFSET 0		#define AHCI_CL_OFFSET 0
#define AHCI_CL_SIZE 32		#define AHCI_CL_SIZE 32
/* Command tables. Up to 32 commands, Each, 128byte aligned. */		/* Command tables. Up to 32 commands, Each, 128byte aligned. */
#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)		#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)		#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
/* Total main work area. */		/* Total main work area. */
#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)		#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
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#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1)		#define AHCI_PRD_MAX (AHCI_PRD_MASK + 1)
#define AHCI_PRD_IPC (1U << 31)		#define AHCI_PRD_IPC (1U << 31)
} __packed;		} __packed;

struct ahci_cmd_tab {		struct ahci_cmd_tab {
u_int8_t cfis[64];		u_int8_t cfis[64];
u_int8_t acmd[32];		u_int8_t acmd[32];
u_int8_t reserved[32];		u_int8_t reserved[32];
struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES];		struct ahci_dma_prd prd_tab[];
} __packed;		} __packed;

struct ahci_cmd_list {		struct ahci_cmd_list {
u_int16_t cmd_flags;		u_int16_t cmd_flags;
#define AHCI_CMD_ATAPI 0x0020		#define AHCI_CMD_ATAPI 0x0020
#define AHCI_CMD_WRITE 0x0040		#define AHCI_CMD_WRITE 0x0040
#define AHCI_CMD_PREFETCH 0x0080		#define AHCI_CMD_PREFETCH 0x0080
#define AHCI_CMD_RESET 0x0100		#define AHCI_CMD_RESET 0x0100
Show All 33 Lines	enum ahci_slot_states {
AHCI_SLOT_RUNNING,		AHCI_SLOT_RUNNING,
AHCI_SLOT_EXECUTING		AHCI_SLOT_EXECUTING
};		};

struct ahci_slot {		struct ahci_slot {
struct ahci_channel ch; / Channel */		struct ahci_channel ch; / Channel */
u_int8_t slot; /* Number of this slot */		u_int8_t slot; /* Number of this slot */
enum ahci_slot_states state; /* Slot state */		enum ahci_slot_states state; /* Slot state */
		u_int ct_offset; /* cmd_tab offset */
union ccb ccb; / CCB occupying slot */		union ccb ccb; / CCB occupying slot */
struct ata_dmaslot dma; /* DMA data of this slot */		struct ata_dmaslot dma; /* DMA data of this slot */
struct callout timeout; /* Execution timeout */		struct callout timeout; /* Execution timeout */
};		};

struct ahci_device {		struct ahci_device {
int revision;		int revision;
int mode;		int mode;
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