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head/usr.sbin/bhyve/pci_xhci.c
Show First 20 Lines • Show All 2,245 Lines • ▼ Show 20 Lines | pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, | ||||
int baridx, uint64_t offset, int size, uint64_t value) | int baridx, uint64_t offset, int size, uint64_t value) | ||||
{ | { | ||||
struct pci_xhci_softc *sc; | struct pci_xhci_softc *sc; | ||||
sc = pi->pi_arg; | sc = pi->pi_arg; | ||||
assert(baridx == 0); | assert(baridx == 0); | ||||
pthread_mutex_lock(&sc->mtx); | pthread_mutex_lock(&sc->mtx); | ||||
if (offset < XHCI_CAPLEN) /* read only registers */ | if (offset < XHCI_CAPLEN) /* read only registers */ | ||||
WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset)); | WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset)); | ||||
else if (offset < sc->dboff) | else if (offset < sc->dboff) | ||||
pci_xhci_hostop_write(sc, offset, value); | pci_xhci_hostop_write(sc, offset, value); | ||||
else if (offset < sc->rtsoff) | else if (offset < sc->rtsoff) | ||||
pci_xhci_dbregs_write(sc, offset, value); | pci_xhci_dbregs_write(sc, offset, value); | ||||
else if (offset < sc->regsend) | else if (offset < sc->regsend) | ||||
▲ Show 20 Lines • Show All 713 Lines • ▼ Show 20 Lines | pci_xhci_snapshot(struct vm_snapshot_meta *meta) | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->opregs.pgsz, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->opregs.pgsz, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->opregs.dnctrl, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->opregs.dnctrl, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->opregs.crcr, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->opregs.crcr, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->opregs.dcbaap, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->opregs.dcbaap, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->opregs.config, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->opregs.config, meta, ret, done); | ||||
/* opregs.cr_p */ | /* opregs.cr_p */ | ||||
SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->opregs.cr_p, | SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->opregs.cr_p, | ||||
XHCI_GADDR_SIZE(sc->opregs.cr_p), false, meta, ret, done); | XHCI_GADDR_SIZE(sc->opregs.cr_p), true, meta, ret, done); | ||||
/* opregs.dcbaa_p */ | /* opregs.dcbaa_p */ | ||||
SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->opregs.dcbaa_p, | SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->opregs.dcbaa_p, | ||||
XHCI_GADDR_SIZE(sc->opregs.dcbaa_p), false, meta, ret, done); | XHCI_GADDR_SIZE(sc->opregs.dcbaa_p), true, meta, ret, done); | ||||
/* rtsregs */ | /* rtsregs */ | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.mfindex, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.mfindex, meta, ret, done); | ||||
/* rtsregs.intrreg */ | /* rtsregs.intrreg */ | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.iman, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.iman, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.imod, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.imod, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erstsz, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erstsz, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.rsvd, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.rsvd, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erstba, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erstba, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erdp, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.intrreg.erdp, meta, ret, done); | ||||
/* rtsregs.erstba_p */ | /* rtsregs.erstba_p */ | ||||
SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->rtsregs.erstba_p, | SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->rtsregs.erstba_p, | ||||
XHCI_GADDR_SIZE(sc->rtsregs.erstba_p), false, meta, ret, done); | XHCI_GADDR_SIZE(sc->rtsregs.erstba_p), true, meta, ret, done); | ||||
/* rtsregs.erst_p */ | /* rtsregs.erst_p */ | ||||
SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->rtsregs.erst_p, | SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(sc->rtsregs.erst_p, | ||||
XHCI_GADDR_SIZE(sc->rtsregs.erst_p), false, meta, ret, done); | XHCI_GADDR_SIZE(sc->rtsregs.erst_p), true, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_deq_seg, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_deq_seg, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_enq_idx, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_enq_idx, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_enq_seg, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_enq_seg, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_events_cnt, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.er_events_cnt, meta, ret, done); | ||||
SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.event_pcs, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(sc->rtsregs.event_pcs, meta, ret, done); | ||||
/* sanity checking */ | /* sanity checking */ | ||||
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines | if (meta->op == VM_SNAPSHOT_SAVE) { | ||||
ret = EINVAL; | ret = EINVAL; | ||||
goto done; | goto done; | ||||
} | } | ||||
if (dev == NULL) | if (dev == NULL) | ||||
continue; | continue; | ||||
SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(dev->dev_ctx, | SNAPSHOT_GUEST2HOST_ADDR_OR_LEAVE(dev->dev_ctx, | ||||
XHCI_GADDR_SIZE(dev->dev_ctx), false, meta, ret, done); | XHCI_GADDR_SIZE(dev->dev_ctx), true, meta, ret, done); | ||||
if (dev->dev_ctx != NULL) { | |||||
for (j = 1; j < XHCI_MAX_ENDPOINTS; j++) { | for (j = 1; j < XHCI_MAX_ENDPOINTS; j++) { | ||||
ret = pci_xhci_snapshot_ep(sc, dev, j, meta); | ret = pci_xhci_snapshot_ep(sc, dev, j, meta); | ||||
if (ret != 0) | if (ret != 0) | ||||
goto done; | goto done; | ||||
} | |||||
} | } | ||||
SNAPSHOT_VAR_OR_LEAVE(dev->dev_slotstate, meta, ret, done); | SNAPSHOT_VAR_OR_LEAVE(dev->dev_slotstate, meta, ret, done); | ||||
/* devices[i]->dev_sc */ | /* devices[i]->dev_sc */ | ||||
dev->dev_ue->ue_snapshot(dev->dev_sc, meta); | dev->dev_ue->ue_snapshot(dev->dev_sc, meta); | ||||
/* devices[i]->hci */ | /* devices[i]->hci */ | ||||
Show All 23 Lines |