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sys/dev/mrsas/mrsas.h
Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines | |||||
#define MRSAS_PRL11 (1 << 5) | #define MRSAS_PRL11 (1 << 5) | ||||
#define mrsas_dprint(sc, level, msg, args...) \ | #define mrsas_dprint(sc, level, msg, args...) \ | ||||
do { \ | do { \ | ||||
if (sc->mrsas_debug & level) \ | if (sc->mrsas_debug & level) \ | ||||
device_printf(sc->mrsas_dev, msg, ##args); \ | device_printf(sc->mrsas_dev, msg, ##args); \ | ||||
} while (0) | } while (0) | ||||
#define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0) | |||||
#define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x)); } while (0) | |||||
/**************************************************************************** | /**************************************************************************** | ||||
* Raid Context structure which describes MegaRAID specific IO Paramenters | * Raid Context structure which describes MegaRAID specific IO Paramenters | ||||
* This resides at offset 0x60 where the SGL normally starts in MPT IO Frames | * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames | ||||
****************************************************************************/ | ****************************************************************************/ | ||||
typedef struct _RAID_CONTEXT { | typedef struct _RAID_CONTEXT { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int8_t Type:4; | u_int8_t Type:4; | ||||
u_int8_t nseg:4; | u_int8_t nseg:4; | ||||
#else | |||||
u_int8_t nseg:4; | |||||
u_int8_t Type:4; | |||||
#endif | |||||
u_int8_t resvd0; | u_int8_t resvd0; | ||||
u_int16_t timeoutValue; | u_int16_t timeoutValue; | ||||
u_int8_t regLockFlags; | u_int8_t regLockFlags; | ||||
u_int8_t resvd1; | u_int8_t resvd1; | ||||
u_int16_t VirtualDiskTgtId; | u_int16_t VirtualDiskTgtId; | ||||
u_int64_t regLockRowLBA; | u_int64_t regLockRowLBA; | ||||
u_int32_t regLockLength; | u_int32_t regLockLength; | ||||
u_int16_t nextLMId; | u_int16_t nextLMId; | ||||
u_int8_t exStatus; | u_int8_t exStatus; | ||||
u_int8_t status; | u_int8_t status; | ||||
u_int8_t RAIDFlags; | u_int8_t RAIDFlags; | ||||
u_int8_t numSGE; | u_int8_t numSGE; | ||||
u_int16_t configSeqNum; | u_int16_t configSeqNum; | ||||
u_int8_t spanArm; | u_int8_t spanArm; | ||||
u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ | u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ | ||||
u_int8_t numSGEExt; /* 0x1E 1M IO support */ | u_int8_t numSGEExt; /* 0x1E 1M IO support */ | ||||
u_int8_t resvd2; /* 0x1F */ | u_int8_t resvd2; /* 0x1F */ | ||||
} RAID_CONTEXT; | } RAID_CONTEXT; | ||||
/* | /* | ||||
* Raid Context structure which describes ventura MegaRAID specific IO Paramenters | * Raid Context structure which describes ventura MegaRAID specific IO Paramenters | ||||
* This resides at offset 0x60 where the SGL normally starts in MPT IO Frames | * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames | ||||
*/ | */ | ||||
typedef struct _RAID_CONTEXT_G35 { | typedef struct _RAID_CONTEXT_G35 { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t Type:4; | u_int16_t Type:4; | ||||
u_int16_t nseg:4; | u_int16_t nseg:4; | ||||
u_int16_t resvd0:8; | u_int16_t resvd0:8; | ||||
#else | |||||
u_int16_t resvd0:8; | |||||
u_int16_t nseg:4; | |||||
u_int16_t Type:4; | |||||
#endif | |||||
u_int16_t timeoutValue; | u_int16_t timeoutValue; | ||||
union { | union { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t reserved:1; | u_int16_t reserved:1; | ||||
u_int16_t sld:1; | u_int16_t sld:1; | ||||
u_int16_t c2f:1; | u_int16_t c2f:1; | ||||
u_int16_t fwn:1; | u_int16_t fwn:1; | ||||
u_int16_t sqn:1; | u_int16_t sqn:1; | ||||
u_int16_t sbs:1; | u_int16_t sbs:1; | ||||
u_int16_t rw:1; | u_int16_t rw:1; | ||||
u_int16_t log:1; | u_int16_t log:1; | ||||
u_int16_t cpuSel:4; | u_int16_t cpuSel:4; | ||||
u_int16_t setDivert:4; | u_int16_t setDivert:4; | ||||
#else | |||||
u_int16_t setDivert:4; | |||||
u_int16_t cpuSel:4; | |||||
u_int16_t log:1; | |||||
u_int16_t rw:1; | |||||
u_int16_t sbs:1; | |||||
u_int16_t sqn:1; | |||||
u_int16_t fwn:1; | |||||
u_int16_t c2f:1; | |||||
u_int16_t sld:1; | |||||
u_int16_t reserved:1; | |||||
#endif | |||||
} bits; | } bits; | ||||
u_int16_t s; | u_int16_t s; | ||||
} routingFlags; | } routingFlags; | ||||
u_int16_t VirtualDiskTgtId; | u_int16_t VirtualDiskTgtId; | ||||
u_int64_t regLockRowLBA; | u_int64_t regLockRowLBA; | ||||
u_int32_t regLockLength; | u_int32_t regLockLength; | ||||
union { | union { | ||||
u_int16_t nextLMId; | u_int16_t nextLMId; | ||||
u_int16_t peerSMID; | u_int16_t peerSMID; | ||||
} smid; | } smid; | ||||
u_int8_t exStatus; | u_int8_t exStatus; | ||||
u_int8_t status; | u_int8_t status; | ||||
u_int8_t RAIDFlags; | u_int8_t RAIDFlags; | ||||
u_int8_t spanArm; | u_int8_t spanArm; | ||||
u_int16_t configSeqNum; | u_int16_t configSeqNum; | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t numSGE:12; | u_int16_t numSGE:12; | ||||
u_int16_t reserved:3; | u_int16_t reserved:3; | ||||
u_int16_t streamDetected:1; | u_int16_t streamDetected:1; | ||||
#else | |||||
u_int16_t streamDetected:1; | |||||
u_int16_t reserved:3; | |||||
u_int16_t numSGE:12; | |||||
#endif | |||||
u_int8_t resvd2[2]; | u_int8_t resvd2[2]; | ||||
} RAID_CONTEXT_G35; | } RAID_CONTEXT_G35; | ||||
typedef union _RAID_CONTEXT_UNION { | typedef union _RAID_CONTEXT_UNION { | ||||
RAID_CONTEXT raid_context; | RAID_CONTEXT raid_context; | ||||
RAID_CONTEXT_G35 raid_context_g35; | RAID_CONTEXT_G35 raid_context_g35; | ||||
} RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; | } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; | ||||
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines | |||||
} MR_TM_REPLY; | } MR_TM_REPLY; | ||||
/* SCSI Task Management Request Message */ | /* SCSI Task Management Request Message */ | ||||
typedef struct _MR_TASK_MANAGE_REQUEST { | typedef struct _MR_TASK_MANAGE_REQUEST { | ||||
/*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ | /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ | ||||
MR_TM_REQUEST TmRequest; | MR_TM_REQUEST TmRequest; | ||||
union { | union { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t isTMForLD:1; | u_int32_t isTMForLD:1; | ||||
u_int32_t isTMForPD:1; | u_int32_t isTMForPD:1; | ||||
u_int32_t reserved1:30; | u_int32_t reserved1:30; | ||||
#else | |||||
u_int32_t reserved1:30; | |||||
u_int32_t isTMForPD:1; | |||||
u_int32_t isTMForLD:1; | |||||
#endif | |||||
u_int32_t reserved2; | u_int32_t reserved2; | ||||
} tmReqFlags; | } tmReqFlags; | ||||
MR_TM_REPLY TMReply; | MR_TM_REPLY TMReply; | ||||
} uTmReqReply; | } uTmReqReply; | ||||
} MR_TASK_MANAGE_REQUEST; | } MR_TASK_MANAGE_REQUEST; | ||||
/* TaskType values */ | /* TaskType values */ | ||||
#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) | #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) | ||||
▲ Show 20 Lines • Show All 356 Lines • ▼ Show 20 Lines | |||||
typedef struct _MR_SPAN_BLOCK_INFO { | typedef struct _MR_SPAN_BLOCK_INFO { | ||||
u_int64_t num_rows; | u_int64_t num_rows; | ||||
MR_LD_SPAN span; | MR_LD_SPAN span; | ||||
MR_SPAN_INFO block_span_info; | MR_SPAN_INFO block_span_info; | ||||
} MR_SPAN_BLOCK_INFO; | } MR_SPAN_BLOCK_INFO; | ||||
typedef struct _MR_LD_RAID { | typedef struct _MR_LD_RAID { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t fpCapable:1; | u_int32_t fpCapable:1; | ||||
u_int32_t raCapable:1; | u_int32_t raCapable:1; | ||||
u_int32_t reserved5:2; | u_int32_t reserved5:2; | ||||
u_int32_t ldPiMode:4; | u_int32_t ldPiMode:4; | ||||
u_int32_t pdPiMode:4; | u_int32_t pdPiMode:4; | ||||
u_int32_t encryptionType:8; | u_int32_t encryptionType:8; | ||||
u_int32_t fpWriteCapable:1; | u_int32_t fpWriteCapable:1; | ||||
u_int32_t fpReadCapable:1; | u_int32_t fpReadCapable:1; | ||||
u_int32_t fpWriteAcrossStripe:1; | u_int32_t fpWriteAcrossStripe:1; | ||||
u_int32_t fpReadAcrossStripe:1; | u_int32_t fpReadAcrossStripe:1; | ||||
u_int32_t fpNonRWCapable:1; | u_int32_t fpNonRWCapable:1; | ||||
u_int32_t tmCapable:1; | u_int32_t tmCapable:1; | ||||
u_int32_t fpCacheBypassCapable:1; | u_int32_t fpCacheBypassCapable:1; | ||||
u_int32_t reserved4:5; | u_int32_t reserved4:5; | ||||
#else | |||||
u_int32_t reserved4:5; | |||||
u_int32_t fpCacheBypassCapable:1; | |||||
u_int32_t tmCapable:1; | |||||
u_int32_t fpNonRWCapable:1; | |||||
u_int32_t fpReadAcrossStripe:1; | |||||
u_int32_t fpWriteAcrossStripe:1; | |||||
u_int32_t fpReadCapable:1; | |||||
u_int32_t fpWriteCapable:1; | |||||
u_int32_t encryptionType:8; | |||||
u_int32_t pdPiMode:4; | |||||
u_int32_t ldPiMode:4; | |||||
u_int32_t reserved5:2; | |||||
u_int32_t raCapable:1; | |||||
u_int32_t fpCapable:1; | |||||
#endif | |||||
} capability; | } capability; | ||||
u_int32_t reserved6; | u_int32_t reserved6; | ||||
u_int64_t size; | u_int64_t size; | ||||
u_int8_t spanDepth; | u_int8_t spanDepth; | ||||
u_int8_t level; | u_int8_t level; | ||||
u_int8_t stripeShift; | u_int8_t stripeShift; | ||||
u_int8_t rowSize; | u_int8_t rowSize; | ||||
u_int8_t rowDataSize; | u_int8_t rowDataSize; | ||||
u_int8_t writeMode; | u_int8_t writeMode; | ||||
u_int8_t PRL; | u_int8_t PRL; | ||||
u_int8_t SRL; | u_int8_t SRL; | ||||
u_int16_t targetId; | u_int16_t targetId; | ||||
u_int8_t ldState; | u_int8_t ldState; | ||||
u_int8_t regTypeReqOnWrite; | u_int8_t regTypeReqOnWrite; | ||||
u_int8_t modFactor; | u_int8_t modFactor; | ||||
u_int8_t regTypeReqOnRead; | u_int8_t regTypeReqOnRead; | ||||
u_int16_t seqNum; | u_int16_t seqNum; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t reserved:30; | |||||
u_int32_t regTypeReqOnReadLsValid:1; | |||||
u_int32_t ldSyncRequired:1; | u_int32_t ldSyncRequired:1; | ||||
#else | |||||
u_int32_t ldSyncRequired:1; | |||||
u_int32_t regTypeReqOnReadLsValid:1; | u_int32_t regTypeReqOnReadLsValid:1; | ||||
u_int32_t reserved:30; | u_int32_t reserved:30; | ||||
#endif | |||||
} flags; | } flags; | ||||
u_int8_t LUN[8]; | u_int8_t LUN[8]; | ||||
u_int8_t fpIoTimeoutForLd; | u_int8_t fpIoTimeoutForLd; | ||||
u_int8_t reserved2[3]; | u_int8_t reserved2[3]; | ||||
u_int32_t logicalBlockLength; | u_int32_t logicalBlockLength; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t reserved1:24; | |||||
u_int32_t LdLogicalBlockExp:4; | |||||
u_int32_t LdPiExp:4; | u_int32_t LdPiExp:4; | ||||
#else | |||||
u_int32_t LdPiExp:4; | |||||
u_int32_t LdLogicalBlockExp:4; | u_int32_t LdLogicalBlockExp:4; | ||||
u_int32_t reserved1:24; | u_int32_t reserved1:24; | ||||
#endif | |||||
} exponent; | } exponent; | ||||
u_int8_t reserved3[0x80 - 0x38]; | u_int8_t reserved3[0x80 - 0x38]; | ||||
} MR_LD_RAID; | } MR_LD_RAID; | ||||
typedef struct _MR_LD_SPAN_MAP { | typedef struct _MR_LD_SPAN_MAP { | ||||
MR_LD_RAID ldRaid; | MR_LD_RAID ldRaid; | ||||
u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; | u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; | ||||
MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; | MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; | ||||
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines | |||||
/* | /* | ||||
* define MR_PD_CFG_SEQ structure for system PDs | * define MR_PD_CFG_SEQ structure for system PDs | ||||
*/ | */ | ||||
struct MR_PD_CFG_SEQ { | struct MR_PD_CFG_SEQ { | ||||
u_int16_t seqNum; | u_int16_t seqNum; | ||||
u_int16_t devHandle; | u_int16_t devHandle; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int8_t tmCapable:1; | u_int8_t tmCapable:1; | ||||
u_int8_t reserved:7; | u_int8_t reserved:7; | ||||
#else | |||||
u_int8_t reserved:7; | |||||
u_int8_t tmCapable:1; | |||||
#endif | |||||
} capability; | } capability; | ||||
u_int8_t reserved; | u_int8_t reserved; | ||||
u_int16_t pdTargetId; | u_int16_t pdTargetId; | ||||
} __packed; | } __packed; | ||||
struct MR_PD_CFG_SEQ_NUM_SYNC { | struct MR_PD_CFG_SEQ_NUM_SYNC { | ||||
u_int32_t size; | u_int32_t size; | ||||
u_int32_t count; | u_int32_t count; | ||||
▲ Show 20 Lines • Show All 811 Lines • ▼ Show 20 Lines | struct mrsas_ctrl_prop { | ||||
u_int8_t loadBalanceMode; | u_int8_t loadBalanceMode; | ||||
u_int8_t disableAutoDetectBackplane; | u_int8_t disableAutoDetectBackplane; | ||||
u_int8_t snapVDSpace; | u_int8_t snapVDSpace; | ||||
/* | /* | ||||
* Add properties that can be controlled by a bit in the following | * Add properties that can be controlled by a bit in the following | ||||
* structure. | * structure. | ||||
*/ | */ | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t copyBackDisabled:1; | u_int32_t copyBackDisabled:1; | ||||
u_int32_t SMARTerEnabled:1; | u_int32_t SMARTerEnabled:1; | ||||
u_int32_t prCorrectUnconfiguredAreas:1; | u_int32_t prCorrectUnconfiguredAreas:1; | ||||
u_int32_t useFdeOnly:1; | u_int32_t useFdeOnly:1; | ||||
u_int32_t disableNCQ:1; | u_int32_t disableNCQ:1; | ||||
u_int32_t SSDSMARTerEnabled:1; | u_int32_t SSDSMARTerEnabled:1; | ||||
u_int32_t SSDPatrolReadEnabled:1; | u_int32_t SSDPatrolReadEnabled:1; | ||||
u_int32_t enableSpinDownUnconfigured:1; | u_int32_t enableSpinDownUnconfigured:1; | ||||
Show All 15 Lines | #if _BYTE_ORDER == _LITTLE_ENDIAN | ||||
u_int32_t enableVirtualCache:1; | u_int32_t enableVirtualCache:1; | ||||
u_int32_t enableAutoLockRecovery:1; | u_int32_t enableAutoLockRecovery:1; | ||||
u_int32_t disableImmediateIO:1; | u_int32_t disableImmediateIO:1; | ||||
u_int32_t disableT10RebuildAssist:1; | u_int32_t disableT10RebuildAssist:1; | ||||
u_int32_t ignore64ldRestriction:1; | u_int32_t ignore64ldRestriction:1; | ||||
u_int32_t enableSwZone:1; | u_int32_t enableSwZone:1; | ||||
u_int32_t limitMaxRateSATA3G:1; | u_int32_t limitMaxRateSATA3G:1; | ||||
u_int32_t reserved:2; | u_int32_t reserved:2; | ||||
#else | |||||
u_int32_t reserved:2; | |||||
u_int32_t limitMaxRateSATA3G:1; | |||||
u_int32_t enableSwZone:1; | |||||
u_int32_t ignore64ldRestriction:1; | |||||
u_int32_t disableT10RebuildAssist:1; | |||||
u_int32_t disableImmediateIO:1; | |||||
u_int32_t enableAutoLockRecovery:1; | |||||
u_int32_t enableVirtualCache:1; | |||||
u_int32_t enableConfigAutoBalance:1; | |||||
u_int32_t forceSGPIOForQuadOnly:1; | |||||
u_int32_t useEmergencySparesforSMARTer:1; | |||||
u_int32_t useUnconfGoodForEmergency:1; | |||||
u_int32_t useGlobalSparesForEmergency:1; | |||||
u_int32_t preventPIImport:1; | |||||
u_int32_t enablePI:1; | |||||
u_int32_t useDiskActivityForLocate:1; | |||||
u_int32_t disableCacheBypass:1; | |||||
u_int32_t enableJBOD:1; | |||||
u_int32_t disableSpinDownHS:1; | |||||
u_int32_t allowBootWithPinnedCache:1; | |||||
u_int32_t disableOnlineCtrlReset:1; | |||||
u_int32_t enableSecretKeyControl:1; | |||||
u_int32_t autoEnhancedImport:1; | |||||
u_int32_t enableSpinDownUnconfigured:1; | |||||
u_int32_t SSDPatrolReadEnabled:1; | |||||
u_int32_t SSDSMARTerEnabled:1; | |||||
u_int32_t disableNCQ:1; | |||||
u_int32_t useFdeOnly:1; | |||||
u_int32_t prCorrectUnconfiguredAreas:1; | |||||
u_int32_t SMARTerEnabled:1; | |||||
u_int32_t copyBackDisabled:1; | |||||
#endif | |||||
} OnOffProperties; | } OnOffProperties; | ||||
u_int8_t autoSnapVDSpace; | u_int8_t autoSnapVDSpace; | ||||
u_int8_t viewSpace; | u_int8_t viewSpace; | ||||
u_int16_t spinDownTime; | u_int16_t spinDownTime; | ||||
u_int8_t reserved[24]; | u_int8_t reserved[24]; | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Lines | struct mrsas_ctrl_info { | ||||
char expanderFwVersion[12]; /* 0x794 */ | char expanderFwVersion[12]; /* 0x794 */ | ||||
u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ | u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ | ||||
u_int16_t cacheMemorySize; /* 0x7A2 */ | u_int16_t cacheMemorySize; /* 0x7A2 */ | ||||
struct { /* 0x7A4 */ | struct { /* 0x7A4 */ | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t supportPIcontroller:1; | u_int32_t supportPIcontroller:1; | ||||
u_int32_t supportLdPIType1:1; | u_int32_t supportLdPIType1:1; | ||||
u_int32_t supportLdPIType2:1; | u_int32_t supportLdPIType2:1; | ||||
u_int32_t supportLdPIType3:1; | u_int32_t supportLdPIType3:1; | ||||
u_int32_t supportLdBBMInfo:1; | u_int32_t supportLdBBMInfo:1; | ||||
u_int32_t supportShieldState:1; | u_int32_t supportShieldState:1; | ||||
u_int32_t blockSSDWriteCacheChange:1; | u_int32_t blockSSDWriteCacheChange:1; | ||||
u_int32_t supportSuspendResumeBGops:1; | u_int32_t supportSuspendResumeBGops:1; | ||||
u_int32_t supportEmergencySpares:1; | u_int32_t supportEmergencySpares:1; | ||||
u_int32_t supportSetLinkSpeed:1; | u_int32_t supportSetLinkSpeed:1; | ||||
u_int32_t supportBootTimePFKChange:1; | u_int32_t supportBootTimePFKChange:1; | ||||
u_int32_t supportJBOD:1; | u_int32_t supportJBOD:1; | ||||
u_int32_t disableOnlinePFKChange:1; | u_int32_t disableOnlinePFKChange:1; | ||||
u_int32_t supportPerfTuning:1; | u_int32_t supportPerfTuning:1; | ||||
u_int32_t supportSSDPatrolRead:1; | u_int32_t supportSSDPatrolRead:1; | ||||
u_int32_t realTimeScheduler:1; | u_int32_t realTimeScheduler:1; | ||||
u_int32_t supportResetNow:1; | u_int32_t supportResetNow:1; | ||||
u_int32_t supportEmulatedDrives:1; | u_int32_t supportEmulatedDrives:1; | ||||
u_int32_t headlessMode:1; | u_int32_t headlessMode:1; | ||||
u_int32_t dedicatedHotSparesLimited:1; | u_int32_t dedicatedHotSparesLimited:1; | ||||
u_int32_t supportUnevenSpans:1; | u_int32_t supportUnevenSpans:1; | ||||
u_int32_t reserved:11; | u_int32_t reserved:11; | ||||
#else | |||||
u_int32_t reserved:11; | |||||
u_int32_t supportUnevenSpans:1; | |||||
u_int32_t dedicatedHotSparesLimited:1; | |||||
u_int32_t headlessMode:1; | |||||
u_int32_t supportEmulatedDrives:1; | |||||
u_int32_t supportResetNow:1; | |||||
u_int32_t realTimeScheduler:1; | |||||
u_int32_t supportSSDPatrolRead:1; | |||||
u_int32_t supportPerfTuning:1; | |||||
u_int32_t disableOnlinePFKChange:1; | |||||
u_int32_t supportJBOD:1; | |||||
u_int32_t supportBootTimePFKChange:1; | |||||
u_int32_t supportSetLinkSpeed:1; | |||||
u_int32_t supportEmergencySpares:1; | |||||
u_int32_t supportSuspendResumeBGops:1; | |||||
u_int32_t blockSSDWriteCacheChange:1; | |||||
u_int32_t supportShieldState:1; | |||||
u_int32_t supportLdBBMInfo:1; | |||||
u_int32_t supportLdPIType3:1; | |||||
u_int32_t supportLdPIType2:1; | |||||
u_int32_t supportLdPIType1:1; | |||||
u_int32_t supportPIcontroller:1; | |||||
#endif | |||||
} adapterOperations2; | } adapterOperations2; | ||||
u_int8_t driverVersion[32]; /* 0x7A8 */ | u_int8_t driverVersion[32]; /* 0x7A8 */ | ||||
u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ | u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ | ||||
u_int8_t temperatureROC; /* 0x7C9 */ | u_int8_t temperatureROC; /* 0x7C9 */ | ||||
u_int8_t temperatureCtrl; /* 0x7CA */ | u_int8_t temperatureCtrl; /* 0x7CA */ | ||||
u_int8_t reserved4; /* 0x7CB */ | u_int8_t reserved4; /* 0x7CB */ | ||||
u_int16_t maxConfigurablePds; /* 0x7CC */ | u_int16_t maxConfigurablePds; /* 0x7CC */ | ||||
u_int8_t reserved5[2]; /* 0x7CD reserved */ | u_int8_t reserved5[2]; /* 0x7CD reserved */ | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t peerIsPresent:1; | u_int32_t peerIsPresent:1; | ||||
u_int32_t peerIsIncompatible:1; | u_int32_t peerIsIncompatible:1; | ||||
u_int32_t hwIncompatible:1; | u_int32_t hwIncompatible:1; | ||||
u_int32_t fwVersionMismatch:1; | u_int32_t fwVersionMismatch:1; | ||||
u_int32_t ctrlPropIncompatible:1; | u_int32_t ctrlPropIncompatible:1; | ||||
u_int32_t premiumFeatureMismatch:1; | u_int32_t premiumFeatureMismatch:1; | ||||
u_int32_t reserved:26; | u_int32_t reserved:26; | ||||
#else | |||||
u_int32_t reserved:26; | |||||
u_int32_t premiumFeatureMismatch:1; | |||||
u_int32_t ctrlPropIncompatible:1; | |||||
u_int32_t fwVersionMismatch:1; | |||||
u_int32_t hwIncompatible:1; | |||||
u_int32_t peerIsIncompatible:1; | |||||
u_int32_t peerIsPresent:1; | |||||
#endif | |||||
} cluster; | } cluster; | ||||
char clusterId[16]; /* 0x7D4 */ | char clusterId[16]; /* 0x7D4 */ | ||||
char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ | char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ | ||||
struct { /* 0x7E8 */ | struct { /* 0x7E8 */ | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t supportPersonalityChange:2; | u_int32_t supportPersonalityChange:2; | ||||
u_int32_t supportThermalPollInterval:1; | u_int32_t supportThermalPollInterval:1; | ||||
u_int32_t supportDisableImmediateIO:1; | u_int32_t supportDisableImmediateIO:1; | ||||
u_int32_t supportT10RebuildAssist:1; | u_int32_t supportT10RebuildAssist:1; | ||||
u_int32_t supportMaxExtLDs:1; | u_int32_t supportMaxExtLDs:1; | ||||
u_int32_t supportCrashDump:1; | u_int32_t supportCrashDump:1; | ||||
u_int32_t supportSwZone:1; | u_int32_t supportSwZone:1; | ||||
u_int32_t supportDebugQueue:1; | u_int32_t supportDebugQueue:1; | ||||
Show All 9 Lines | #if _BYTE_ORDER == _LITTLE_ENDIAN | ||||
u_int32_t supportSecurityonJBOD:1; | u_int32_t supportSecurityonJBOD:1; | ||||
u_int32_t discardCacheDuringLDDelete:1; | u_int32_t discardCacheDuringLDDelete:1; | ||||
u_int32_t supportTTYLogCompression:1; | u_int32_t supportTTYLogCompression:1; | ||||
u_int32_t supportCPLDUpdate:1; | u_int32_t supportCPLDUpdate:1; | ||||
u_int32_t supportDiskCacheSettingForSysPDs:1; | u_int32_t supportDiskCacheSettingForSysPDs:1; | ||||
u_int32_t supportExtendedSSCSize:1; | u_int32_t supportExtendedSSCSize:1; | ||||
u_int32_t useSeqNumJbodFP:1; | u_int32_t useSeqNumJbodFP:1; | ||||
u_int32_t reserved:7; | u_int32_t reserved:7; | ||||
#else | |||||
u_int32_t reserved:7; | |||||
u_int32_t useSeqNumJbodFP:1; | |||||
u_int32_t supportExtendedSSCSize:1; | |||||
u_int32_t supportDiskCacheSettingForSysPDs:1; | |||||
u_int32_t supportCPLDUpdate:1; | |||||
u_int32_t supportTTYLogCompression:1; | |||||
u_int32_t discardCacheDuringLDDelete:1; | |||||
u_int32_t supportSecurityonJBOD:1; | |||||
u_int32_t supportCacheBypassModes:1; | |||||
u_int32_t supportDisableSESMonitoring:1; | |||||
u_int32_t supportForceFlash:1; | |||||
u_int32_t supportNVDRAM:1; | |||||
u_int32_t supportDrvActivityLEDSetting:1; | |||||
u_int32_t supportAllowedOpsforDrvRemoval:1; | |||||
u_int32_t supportHOQRebuild:1; | |||||
u_int32_t supportForceTo512e:1; | |||||
u_int32_t supportNVCacheErase:1; | |||||
u_int32_t supportDebugQueue:1; | |||||
u_int32_t supportSwZone:1; | |||||
u_int32_t supportCrashDump:1; | |||||
u_int32_t supportMaxExtLDs:1; | |||||
u_int32_t supportT10RebuildAssist:1; | |||||
u_int32_t supportDisableImmediateIO:1; | |||||
u_int32_t supportThermalPollInterval:1; | |||||
u_int32_t supportPersonalityChange:2; | |||||
#endif | |||||
} adapterOperations3; | } adapterOperations3; | ||||
u_int8_t pad_cpld[16]; | u_int8_t pad_cpld[16]; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t ctrlInfoExtSupported:1; | u_int16_t ctrlInfoExtSupported:1; | ||||
u_int16_t supportIbuttonLess:1; | u_int16_t supportIbuttonLess:1; | ||||
u_int16_t supportedEncAlgo:1; | u_int16_t supportedEncAlgo:1; | ||||
u_int16_t supportEncryptedMfc:1; | u_int16_t supportEncryptedMfc:1; | ||||
u_int16_t imageUploadSupported:1; | u_int16_t imageUploadSupported:1; | ||||
u_int16_t supportSESCtrlInMultipathCfg:1; | u_int16_t supportSESCtrlInMultipathCfg:1; | ||||
u_int16_t supportPdMapTargetId:1; | u_int16_t supportPdMapTargetId:1; | ||||
u_int16_t FWSwapsBBUVPDInfo:1; | u_int16_t FWSwapsBBUVPDInfo:1; | ||||
u_int16_t reserved:8; | u_int16_t reserved:8; | ||||
#else | |||||
u_int16_t reserved:8; | |||||
u_int16_t FWSwapsBBUVPDInfo:1; | |||||
u_int16_t supportPdMapTargetId:1; | |||||
u_int16_t supportSESCtrlInMultipathCfg:1; | |||||
u_int16_t imageUploadSupported:1; | |||||
u_int16_t supportEncryptedMfc:1; | |||||
u_int16_t supportedEncAlgo:1; | |||||
u_int16_t supportIbuttonLess:1; | |||||
u_int16_t ctrlInfoExtSupported:1; | |||||
#endif | |||||
} adapterOperations4; | } adapterOperations4; | ||||
u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ | u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ | ||||
} __packed; | } __packed; | ||||
/* | /* | ||||
* When SCSI mid-layer calls driver's reset routine, driver waits for | * When SCSI mid-layer calls driver's reset routine, driver waits for | ||||
* MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note | * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note | ||||
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines | |||||
#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 | #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 | ||||
#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) | #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) | ||||
#define MFI_1068_PCSR_OFFSET 0x84 | #define MFI_1068_PCSR_OFFSET 0x84 | ||||
#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 | #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 | ||||
#define MFI_1068_FW_READY 0xDDDD0000 | #define MFI_1068_FW_READY 0xDDDD0000 | ||||
typedef union _MFI_CAPABILITIES { | typedef union _MFI_CAPABILITIES { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t support_fp_remote_lun:1; | u_int32_t support_fp_remote_lun:1; | ||||
u_int32_t support_additional_msix:1; | u_int32_t support_additional_msix:1; | ||||
u_int32_t support_fastpath_wb:1; | u_int32_t support_fastpath_wb:1; | ||||
u_int32_t support_max_255lds:1; | u_int32_t support_max_255lds:1; | ||||
u_int32_t support_ndrive_r1_lb:1; | u_int32_t support_ndrive_r1_lb:1; | ||||
u_int32_t support_core_affinity:1; | u_int32_t support_core_affinity:1; | ||||
u_int32_t security_protocol_cmds_fw:1; | u_int32_t security_protocol_cmds_fw:1; | ||||
u_int32_t support_ext_queue_depth:1; | u_int32_t support_ext_queue_depth:1; | ||||
u_int32_t support_ext_io_size:1; | u_int32_t support_ext_io_size:1; | ||||
u_int32_t reserved:23; | u_int32_t reserved:23; | ||||
#else | |||||
u_int32_t reserved:23; | |||||
u_int32_t support_ext_io_size:1; | |||||
u_int32_t support_ext_queue_depth:1; | |||||
u_int32_t security_protocol_cmds_fw:1; | |||||
u_int32_t support_core_affinity:1; | |||||
u_int32_t support_ndrive_r1_lb:1; | |||||
u_int32_t support_max_255lds:1; | |||||
u_int32_t support_fastpath_wb:1; | |||||
u_int32_t support_additional_msix:1; | |||||
u_int32_t support_fp_remote_lun:1; | |||||
#endif | |||||
} mfi_capabilities; | } mfi_capabilities; | ||||
u_int32_t reg; | u_int32_t reg; | ||||
} MFI_CAPABILITIES; | } MFI_CAPABILITIES; | ||||
#pragma pack(1) | #pragma pack(1) | ||||
struct mrsas_sge32 { | struct mrsas_sge32 { | ||||
u_int32_t phys_addr; | u_int32_t phys_addr; | ||||
u_int32_t length; | u_int32_t length; | ||||
▲ Show 20 Lines • Show All 244 Lines • ▼ Show 20 Lines | union mrsas_frame { | ||||
struct mrsas_smp_frame smp; | struct mrsas_smp_frame smp; | ||||
struct mrsas_stp_frame stp; | struct mrsas_stp_frame stp; | ||||
u_int8_t raw_bytes[64]; | u_int8_t raw_bytes[64]; | ||||
}; | }; | ||||
#pragma pack(1) | #pragma pack(1) | ||||
union mrsas_evt_class_locale { | union mrsas_evt_class_locale { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t locale; | u_int16_t locale; | ||||
u_int8_t reserved; | u_int8_t reserved; | ||||
int8_t class; | int8_t class; | ||||
#else | |||||
int8_t class; | |||||
u_int8_t reserved; | |||||
u_int16_t locale; | |||||
#endif | |||||
} __packed members; | } __packed members; | ||||
u_int32_t word; | u_int32_t word; | ||||
} __packed; | } __packed; | ||||
#pragma pack() | #pragma pack() | ||||
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines | |||||
} MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; | } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; | ||||
#define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes | #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes | ||||
typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { | typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { | ||||
union { | union { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t linkSpeed:4; | u_int32_t linkSpeed:4; | ||||
u_int32_t linkWidth:6; | u_int32_t linkWidth:6; | ||||
u_int32_t aspmSupport:2; | u_int32_t aspmSupport:2; | ||||
u_int32_t losExitLatency:3; | u_int32_t losExitLatency:3; | ||||
u_int32_t l1ExitLatency:3; | u_int32_t l1ExitLatency:3; | ||||
u_int32_t rsvdp:6; | u_int32_t rsvdp:6; | ||||
u_int32_t portNumber:8; | u_int32_t portNumber:8; | ||||
#else | |||||
u_int32_t portNumber:8; | |||||
u_int32_t rsvdp:6; | |||||
u_int32_t l1ExitLatency:3; | |||||
u_int32_t losExitLatency:3; | |||||
u_int32_t aspmSupport:2; | |||||
u_int32_t linkWidth:6; | |||||
u_int32_t linkSpeed:4; | |||||
#endif | |||||
} bits; | } bits; | ||||
u_int32_t asUlong; | u_int32_t asUlong; | ||||
} u; | } u; | ||||
} MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; | } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; | ||||
#define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) | #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) | ||||
typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { | typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { | ||||
union { | union { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t linkSpeed:4; | u_int16_t linkSpeed:4; | ||||
u_int16_t negotiatedLinkWidth:6; | u_int16_t negotiatedLinkWidth:6; | ||||
u_int16_t linkTrainingError:1; | u_int16_t linkTrainingError:1; | ||||
u_int16_t linkTraning:1; | u_int16_t linkTraning:1; | ||||
u_int16_t slotClockConfig:1; | u_int16_t slotClockConfig:1; | ||||
u_int16_t rsvdZ:3; | u_int16_t rsvdZ:3; | ||||
#else | |||||
u_int16_t rsvdZ:3; | |||||
u_int16_t slotClockConfig:1; | |||||
u_int16_t linkTraning:1; | |||||
u_int16_t linkTrainingError:1; | |||||
u_int16_t negotiatedLinkWidth:6; | |||||
u_int16_t linkSpeed:4; | |||||
#endif | |||||
} bits; | } bits; | ||||
u_int16_t asUshort; | u_int16_t asUshort; | ||||
} u; | } u; | ||||
u_int16_t reserved; | u_int16_t reserved; | ||||
} MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; | } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; | ||||
#define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) | #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) | ||||
Show All 37 Lines | |||||
/* | /* | ||||
* define the DDF Type bit structure | * define the DDF Type bit structure | ||||
*/ | */ | ||||
union MR_PD_DDF_TYPE { | union MR_PD_DDF_TYPE { | ||||
struct { | struct { | ||||
union { | union { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t forcedPDGUID:1; | u_int16_t forcedPDGUID:1; | ||||
u_int16_t inVD:1; | u_int16_t inVD:1; | ||||
u_int16_t isGlobalSpare:1; | u_int16_t isGlobalSpare:1; | ||||
u_int16_t isSpare:1; | u_int16_t isSpare:1; | ||||
u_int16_t isForeign:1; | u_int16_t isForeign:1; | ||||
u_int16_t reserved:7; | u_int16_t reserved:7; | ||||
u_int16_t intf:4; | u_int16_t intf:4; | ||||
#else | |||||
u_int16_t intf:4; | |||||
u_int16_t reserved:7; | |||||
u_int16_t isForeign:1; | |||||
u_int16_t isSpare:1; | |||||
u_int16_t isGlobalSpare:1; | |||||
u_int16_t inVD:1; | |||||
u_int16_t forcedPDGUID:1; | |||||
#endif | |||||
} pdType; | } pdType; | ||||
u_int16_t type; | u_int16_t type; | ||||
}; | }; | ||||
u_int16_t reserved; | u_int16_t reserved; | ||||
} ddf; | } ddf; | ||||
struct { | struct { | ||||
u_int32_t reserved; | u_int32_t reserved; | ||||
} nonDisk; | } nonDisk; | ||||
Show All 14 Lines | union MR_PROGRESS { | ||||
u_int32_t w; | u_int32_t w; | ||||
} __packed; | } __packed; | ||||
/* | /* | ||||
* defines the physical drive progress structure | * defines the physical drive progress structure | ||||
*/ | */ | ||||
struct MR_PD_PROGRESS { | struct MR_PD_PROGRESS { | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t rbld:1; | u_int32_t rbld:1; | ||||
u_int32_t patrol:1; | u_int32_t patrol:1; | ||||
u_int32_t clear:1; | u_int32_t clear:1; | ||||
u_int32_t copyBack:1; | u_int32_t copyBack:1; | ||||
u_int32_t erase:1; | u_int32_t erase:1; | ||||
u_int32_t locate:1; | u_int32_t locate:1; | ||||
u_int32_t reserved:26; | u_int32_t reserved:26; | ||||
#else | |||||
u_int32_t reserved:26; | |||||
u_int32_t locate:1; | |||||
u_int32_t erase:1; | |||||
u_int32_t copyBack:1; | |||||
u_int32_t clear:1; | |||||
u_int32_t patrol:1; | |||||
u_int32_t rbld:1; | |||||
#endif | |||||
} active; | } active; | ||||
union MR_PROGRESS rbld; | union MR_PROGRESS rbld; | ||||
union MR_PROGRESS patrol; | union MR_PROGRESS patrol; | ||||
union { | union { | ||||
union MR_PROGRESS clear; | union MR_PROGRESS clear; | ||||
union MR_PROGRESS erase; | union MR_PROGRESS erase; | ||||
}; | }; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t rbld:1; | u_int32_t rbld:1; | ||||
u_int32_t patrol:1; | u_int32_t patrol:1; | ||||
u_int32_t clear:1; | u_int32_t clear:1; | ||||
u_int32_t copyBack:1; | u_int32_t copyBack:1; | ||||
u_int32_t erase:1; | u_int32_t erase:1; | ||||
u_int32_t reserved:27; | u_int32_t reserved:27; | ||||
#else | |||||
u_int32_t reserved:27; | |||||
u_int32_t erase:1; | |||||
u_int32_t copyBack:1; | |||||
u_int32_t clear:1; | |||||
u_int32_t patrol:1; | |||||
u_int32_t rbld:1; | |||||
#endif | |||||
} pause; | } pause; | ||||
union MR_PROGRESS reserved[3]; | union MR_PROGRESS reserved[3]; | ||||
} __packed; | } __packed; | ||||
struct mrsas_pd_info { | struct mrsas_pd_info { | ||||
MR_PD_REF ref; | MR_PD_REF ref; | ||||
u_int8_t inquiryData[96]; | u_int8_t inquiryData[96]; | ||||
Show All 15 Lines | struct mrsas_pd_info { | ||||
u_int16_t fwState; | u_int16_t fwState; | ||||
u_int8_t disabledForRemoval; | u_int8_t disabledForRemoval; | ||||
u_int8_t linkSpeed; | u_int8_t linkSpeed; | ||||
union MR_PD_DDF_TYPE state; | union MR_PD_DDF_TYPE state; | ||||
struct { | struct { | ||||
u_int8_t count; | u_int8_t count; | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int8_t isPathBroken:4; | u_int8_t isPathBroken:4; | ||||
u_int8_t reserved3:3; | u_int8_t reserved3:3; | ||||
u_int8_t widePortCapable:1; | u_int8_t widePortCapable:1; | ||||
#else | |||||
u_int8_t widePortCapable:1; | |||||
u_int8_t reserved3:3; | |||||
u_int8_t isPathBroken:4; | |||||
#endif | |||||
u_int8_t connectorIndex[2]; | u_int8_t connectorIndex[2]; | ||||
u_int8_t reserved[4]; | u_int8_t reserved[4]; | ||||
u_int64_t sasAddr[2]; | u_int64_t sasAddr[2]; | ||||
u_int8_t reserved2[16]; | u_int8_t reserved2[16]; | ||||
} pathInfo; | } pathInfo; | ||||
u_int64_t rawSize; | u_int64_t rawSize; | ||||
u_int64_t nonCoercedSize; | u_int64_t nonCoercedSize; | ||||
u_int64_t coercedSize; | u_int64_t coercedSize; | ||||
u_int16_t enclDeviceId; | u_int16_t enclDeviceId; | ||||
u_int8_t enclIndex; | u_int8_t enclIndex; | ||||
union { | union { | ||||
u_int8_t slotNumber; | u_int8_t slotNumber; | ||||
u_int8_t enclConnectorIndex; | u_int8_t enclConnectorIndex; | ||||
}; | }; | ||||
struct MR_PD_PROGRESS progInfo; | struct MR_PD_PROGRESS progInfo; | ||||
u_int8_t badBlockTableFull; | u_int8_t badBlockTableFull; | ||||
u_int8_t unusableInCurrentConfig; | u_int8_t unusableInCurrentConfig; | ||||
u_int8_t vpdPage83Ext[64]; | u_int8_t vpdPage83Ext[64]; | ||||
u_int8_t powerState; | u_int8_t powerState; | ||||
u_int8_t enclPosition; | u_int8_t enclPosition; | ||||
u_int32_t allowedOps; | u_int32_t allowedOps; | ||||
u_int16_t copyBackPartnerId; | u_int16_t copyBackPartnerId; | ||||
u_int16_t enclPartnerDeviceId; | u_int16_t enclPartnerDeviceId; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int16_t fdeCapable:1; | u_int16_t fdeCapable:1; | ||||
u_int16_t fdeEnabled:1; | u_int16_t fdeEnabled:1; | ||||
u_int16_t secured:1; | u_int16_t secured:1; | ||||
u_int16_t locked:1; | u_int16_t locked:1; | ||||
u_int16_t foreign:1; | u_int16_t foreign:1; | ||||
u_int16_t needsEKM:1; | u_int16_t needsEKM:1; | ||||
u_int16_t reserved:10; | u_int16_t reserved:10; | ||||
#else | |||||
u_int16_t reserved:10; | |||||
u_int16_t needsEKM:1; | |||||
u_int16_t foreign:1; | |||||
u_int16_t locked:1; | |||||
u_int16_t secured:1; | |||||
u_int16_t fdeEnabled:1; | |||||
u_int16_t fdeCapable:1; | |||||
#endif | |||||
} security; | } security; | ||||
u_int8_t mediaType; | u_int8_t mediaType; | ||||
u_int8_t notCertified; | u_int8_t notCertified; | ||||
u_int8_t bridgeVendor[8]; | u_int8_t bridgeVendor[8]; | ||||
u_int8_t bridgeProductIdentification[16]; | u_int8_t bridgeProductIdentification[16]; | ||||
u_int8_t bridgeProductRevisionLevel[4]; | u_int8_t bridgeProductRevisionLevel[4]; | ||||
u_int8_t satBridgeExists; | u_int8_t satBridgeExists; | ||||
u_int8_t interfaceType; | u_int8_t interfaceType; | ||||
u_int8_t temperature; | u_int8_t temperature; | ||||
u_int8_t emulatedBlockSize; | u_int8_t emulatedBlockSize; | ||||
u_int16_t userDataBlockSize; | u_int16_t userDataBlockSize; | ||||
u_int16_t reserved2; | u_int16_t reserved2; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t piType:3; | u_int32_t piType:3; | ||||
u_int32_t piFormatted:1; | u_int32_t piFormatted:1; | ||||
u_int32_t piEligible:1; | u_int32_t piEligible:1; | ||||
u_int32_t NCQ:1; | u_int32_t NCQ:1; | ||||
u_int32_t WCE:1; | u_int32_t WCE:1; | ||||
u_int32_t commissionedSpare:1; | u_int32_t commissionedSpare:1; | ||||
u_int32_t emergencySpare:1; | u_int32_t emergencySpare:1; | ||||
u_int32_t ineligibleForSSCD:1; | u_int32_t ineligibleForSSCD:1; | ||||
u_int32_t ineligibleForLd:1; | u_int32_t ineligibleForLd:1; | ||||
u_int32_t useSSEraseType:1; | u_int32_t useSSEraseType:1; | ||||
u_int32_t wceUnchanged:1; | u_int32_t wceUnchanged:1; | ||||
u_int32_t supportScsiUnmap:1; | u_int32_t supportScsiUnmap:1; | ||||
u_int32_t reserved:18; | u_int32_t reserved:18; | ||||
#else | |||||
u_int32_t reserved:18; | |||||
u_int32_t supportScsiUnmap:1; | |||||
u_int32_t wceUnchanged:1; | |||||
u_int32_t useSSEraseType:1; | |||||
u_int32_t ineligibleForLd:1; | |||||
u_int32_t ineligibleForSSCD:1; | |||||
u_int32_t emergencySpare:1; | |||||
u_int32_t commissionedSpare:1; | |||||
u_int32_t WCE:1; | |||||
u_int32_t NCQ:1; | |||||
u_int32_t piEligible:1; | |||||
u_int32_t piFormatted:1; | |||||
u_int32_t piType:3; | |||||
#endif | |||||
} properties; | } properties; | ||||
u_int64_t shieldDiagCompletionTime; | u_int64_t shieldDiagCompletionTime; | ||||
u_int8_t shieldCounter; | u_int8_t shieldCounter; | ||||
u_int8_t linkSpeedOther; | u_int8_t linkSpeedOther; | ||||
u_int8_t reserved4[2]; | u_int8_t reserved4[2]; | ||||
struct { | struct { | ||||
#if _BYTE_ORDER == _LITTLE_ENDIAN | |||||
u_int32_t bbmErrCountSupported:1; | u_int32_t bbmErrCountSupported:1; | ||||
u_int32_t bbmErrCount:31; | u_int32_t bbmErrCount:31; | ||||
#else | |||||
u_int32_t bbmErrCount:31; | |||||
u_int32_t bbmErrCountSupported:1; | |||||
#endif | |||||
} bbmErr; | } bbmErr; | ||||
u_int8_t reserved1[512-428]; | u_int8_t reserved1[512-428]; | ||||
} __packed; | } __packed; | ||||
struct mrsas_target { | struct mrsas_target { | ||||
u_int16_t target_id; | u_int16_t target_id; | ||||
u_int32_t queue_depth; | u_int32_t queue_depth; | ||||
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