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sys/dev/mrsas/mrsas.c
Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines | |||||
#include <cam/cam_ccb.h> | #include <cam/cam_ccb.h> | ||||
#include <sys/sysctl.h> | #include <sys/sysctl.h> | ||||
#include <sys/types.h> | #include <sys/types.h> | ||||
#include <sys/sysent.h> | #include <sys/sysent.h> | ||||
#include <sys/kthread.h> | #include <sys/kthread.h> | ||||
#include <sys/taskqueue.h> | #include <sys/taskqueue.h> | ||||
#include <sys/smp.h> | #include <sys/smp.h> | ||||
#include <sys/endian.h> | |||||
/* | /* | ||||
* Function prototypes | * Function prototypes | ||||
*/ | */ | ||||
static d_open_t mrsas_open; | static d_open_t mrsas_open; | ||||
static d_close_t mrsas_close; | static d_close_t mrsas_close; | ||||
static d_read_t mrsas_read; | static d_read_t mrsas_read; | ||||
static d_write_t mrsas_write; | static d_write_t mrsas_write; | ||||
▲ Show 20 Lines • Show All 551 Lines • ▼ Show 20 Lines | if (mrsas_alloc_evt_log_info_cmd(sc) != SUCCESS) { | ||||
mrsas_release_mfi_cmd(cmd); | mrsas_release_mfi_cmd(cmd); | ||||
return -ENOMEM; | return -ENOMEM; | ||||
} | } | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0x0; | dcmd->cmd_status = 0x0; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = htole16(MFI_FRAME_DIR_READ); | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = sizeof(struct mrsas_evt_log_info); | dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_log_info)); | ||||
dcmd->opcode = MR_DCMD_CTRL_EVENT_GET_INFO; | dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_GET_INFO); | ||||
dcmd->sgl.sge32[0].phys_addr = sc->el_info_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32(sc->el_info_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_log_info); | dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_log_info)); | ||||
retcode = mrsas_issue_blocked_cmd(sc, cmd); | retcode = mrsas_issue_blocked_cmd(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
goto dcmd_timeout; | goto dcmd_timeout; | ||||
do_ocr = 0; | do_ocr = 0; | ||||
/* | /* | ||||
* Copy the data back into callers buffer | * Copy the data back into callers buffer | ||||
Show All 39 Lines | mrsas_register_aen(struct mrsas_softc *sc, u_int32_t seq_num, | ||||
* is _not_ inclusive, then we have to abort that command, form a | * is _not_ inclusive, then we have to abort that command, form a | ||||
* class_locale that is superset of both old and current and re-issue | * class_locale that is superset of both old and current and re-issue | ||||
* to the FW | * to the FW | ||||
*/ | */ | ||||
curr_aen.word = class_locale_word; | curr_aen.word = class_locale_word; | ||||
if (sc->aen_cmd) { | if (sc->aen_cmd) { | ||||
prev_aen.word = sc->aen_cmd->frame->dcmd.mbox.w[1]; | prev_aen.word = le32toh(sc->aen_cmd->frame->dcmd.mbox.w[1]); | ||||
/* | /* | ||||
* A class whose enum value is smaller is inclusive of all | * A class whose enum value is smaller is inclusive of all | ||||
* higher values. If a PROGRESS (= -1) was previously | * higher values. If a PROGRESS (= -1) was previously | ||||
* registered, then a new registration requests for higher | * registered, then a new registration requests for higher | ||||
* classes need not be sent to FW. They are automatically | * classes need not be sent to FW. They are automatically | ||||
* included. Locale numbers don't have such hierarchy. They | * included. Locale numbers don't have such hierarchy. They | ||||
* are bitmap values | * are bitmap values | ||||
Show All 34 Lines | mrsas_register_aen(struct mrsas_softc *sc, u_int32_t seq_num, | ||||
/* | /* | ||||
* Prepare DCMD for aen registration | * Prepare DCMD for aen registration | ||||
*/ | */ | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0x0; | dcmd->cmd_status = 0x0; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = htole16(MFI_FRAME_DIR_READ); | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = sizeof(struct mrsas_evt_detail); | dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_detail)); | ||||
dcmd->opcode = MR_DCMD_CTRL_EVENT_WAIT; | dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_WAIT); | ||||
dcmd->mbox.w[0] = seq_num; | dcmd->mbox.w[0] = htole32(seq_num); | ||||
sc->last_seq_num = seq_num; | sc->last_seq_num = seq_num; | ||||
dcmd->mbox.w[1] = curr_aen.word; | dcmd->mbox.w[1] = htole32(curr_aen.word); | ||||
dcmd->sgl.sge32[0].phys_addr = (u_int32_t)sc->evt_detail_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->evt_detail_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_detail); | dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_detail)); | ||||
if (sc->aen_cmd != NULL) { | if (sc->aen_cmd != NULL) { | ||||
mrsas_release_mfi_cmd(cmd); | mrsas_release_mfi_cmd(cmd); | ||||
return 0; | return 0; | ||||
} | } | ||||
/* | /* | ||||
* Store reference to the cmd used to register for AEN. When an | * Store reference to the cmd used to register for AEN. When an | ||||
* application wants us to register for AEN, we have to abort this | * application wants us to register for AEN, we have to abort this | ||||
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines | mrsas_attach(device_t dev) | ||||
} | } | ||||
mrsas_get_tunables(sc); | mrsas_get_tunables(sc); | ||||
/* | /* | ||||
* Set up PCI and registers | * Set up PCI and registers | ||||
*/ | */ | ||||
cmd = pci_read_config(dev, PCIR_COMMAND, 2); | cmd = pci_read_config(dev, PCIR_COMMAND, 2); | ||||
if ((cmd & PCIM_CMD_PORTEN) == 0) { | |||||
return (ENXIO); | |||||
} | |||||
luporl: Why was this check removed? | |||||
Done Inline ActionsThis check was preventing the driver to continue execution and as it is not present on linux driver 'megaraid' that works on the same card so I removed it from here. I found no issues doing this. afscoelho_gmail.com: This check was preventing the driver to continue execution and as it is not present on linux… | |||||
/* Force the busmaster enable bit on. */ | /* Force the busmaster enable bit on. */ | ||||
cmd |= PCIM_CMD_BUSMASTEREN; | cmd |= PCIM_CMD_BUSMASTEREN; | ||||
pci_write_config(dev, PCIR_COMMAND, cmd, 2); | pci_write_config(dev, PCIR_COMMAND, cmd, 2); | ||||
/* For Ventura/Aero system registers are mapped to BAR0 */ | /* For Ventura/Aero system registers are mapped to BAR0 */ | ||||
if (sc->is_ventura || sc->is_aero) | if (sc->is_ventura || sc->is_aero) | ||||
sc->reg_res_id = PCIR_BAR(0); /* BAR0 offset */ | sc->reg_res_id = PCIR_BAR(0); /* BAR0 offset */ | ||||
else | else | ||||
▲ Show 20 Lines • Show All 778 Lines • ▼ Show 20 Lines | #endif | ||||
desc_val.word = desc->Words; | desc_val.word = desc->Words; | ||||
num_completed = 0; | num_completed = 0; | ||||
reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; | ||||
/* Find our reply descriptor for the command and process */ | /* Find our reply descriptor for the command and process */ | ||||
while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) { | while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) { | ||||
smid = reply_desc->SMID; | smid = le16toh(reply_desc->SMID); | ||||
cmd_mpt = sc->mpt_cmd_list[smid - 1]; | cmd_mpt = sc->mpt_cmd_list[smid - 1]; | ||||
scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request; | scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request; | ||||
status = scsi_io_req->RaidContext.raid_context.status; | status = scsi_io_req->RaidContext.raid_context.status; | ||||
extStatus = scsi_io_req->RaidContext.raid_context.exStatus; | extStatus = scsi_io_req->RaidContext.raid_context.exStatus; | ||||
sense = cmd_mpt->sense; | sense = cmd_mpt->sense; | ||||
data_length = scsi_io_req->DataLength; | data_length = scsi_io_req->DataLength; | ||||
Show All 15 Lines | case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */ | ||||
if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) { | if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) { | ||||
mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]); | mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]); | ||||
cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG; | cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG; | ||||
} | } | ||||
/* Fall thru and complete IO */ | /* Fall thru and complete IO */ | ||||
case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST: | case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST: | ||||
if (cmd_mpt->r1_alt_dev_handle == MR_DEVHANDLE_INVALID) { | if (cmd_mpt->r1_alt_dev_handle == MR_DEVHANDLE_INVALID) { | ||||
mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status, | mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status, | ||||
extStatus, data_length, sense); | extStatus, le32toh(data_length), sense); | ||||
mrsas_cmd_done(sc, cmd_mpt); | mrsas_cmd_done(sc, cmd_mpt); | ||||
mrsas_atomic_dec(&sc->fw_outstanding); | mrsas_atomic_dec(&sc->fw_outstanding); | ||||
} else { | } else { | ||||
/* | /* | ||||
* If the peer Raid 1/10 fast path failed, | * If the peer Raid 1/10 fast path failed, | ||||
* mark IO as failed to the scsi layer. | * mark IO as failed to the scsi layer. | ||||
* Overwrite the current status by the failed status | * Overwrite the current status by the failed status | ||||
* and make sure that if any command fails, | * and make sure that if any command fails, | ||||
Show All 11 Lines | case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST: | ||||
r1_cmd->ccb_ptr = NULL; | r1_cmd->ccb_ptr = NULL; | ||||
if (r1_cmd->callout_owner) { | if (r1_cmd->callout_owner) { | ||||
callout_stop(&r1_cmd->cm_callout); | callout_stop(&r1_cmd->cm_callout); | ||||
r1_cmd->callout_owner = false; | r1_cmd->callout_owner = false; | ||||
} | } | ||||
mrsas_release_mpt_cmd(r1_cmd); | mrsas_release_mpt_cmd(r1_cmd); | ||||
mrsas_atomic_dec(&sc->fw_outstanding); | mrsas_atomic_dec(&sc->fw_outstanding); | ||||
mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status, | mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status, | ||||
extStatus, data_length, sense); | extStatus, le32toh(data_length), sense); | ||||
mrsas_cmd_done(sc, cmd_mpt); | mrsas_cmd_done(sc, cmd_mpt); | ||||
mrsas_atomic_dec(&sc->fw_outstanding); | mrsas_atomic_dec(&sc->fw_outstanding); | ||||
} | } | ||||
} | } | ||||
break; | break; | ||||
case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */ | case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */ | ||||
cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx]; | cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx]; | ||||
/* | /* | ||||
* Make sure NOT TO release the mfi command from the called | * Make sure NOT TO release the mfi command from the called | ||||
* function's context if it is fired with issue_polled call. | * function's context if it is fired with issue_polled call. | ||||
* And also make sure that the issue_polled call should only be | * And also make sure that the issue_polled call should only be | ||||
* used if INTERRUPT IS DISABLED. | * used if INTERRUPT IS DISABLED. | ||||
*/ | */ | ||||
if (cmd_mfi->frame->hdr.flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE) | if (cmd_mfi->frame->hdr.flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)) | ||||
mrsas_release_mfi_cmd(cmd_mfi); | mrsas_release_mfi_cmd(cmd_mfi); | ||||
else | else | ||||
mrsas_complete_mptmfi_passthru(sc, cmd_mfi, status); | mrsas_complete_mptmfi_passthru(sc, cmd_mfi, status); | ||||
break; | break; | ||||
} | } | ||||
sc->last_reply_idx[MSIxIndex]++; | sc->last_reply_idx[MSIxIndex]++; | ||||
if (sc->last_reply_idx[MSIxIndex] >= sc->reply_q_depth) | if (sc->last_reply_idx[MSIxIndex] >= sc->reply_q_depth) | ||||
▲ Show 20 Lines • Show All 798 Lines • ▼ Show 20 Lines | mrsas_init_adapter(struct mrsas_softc *sc) | ||||
/* Determine allocation size of command frames */ | /* Determine allocation size of command frames */ | ||||
sc->reply_q_depth = ((sc->max_fw_cmds + 1 + 15) / 16 * 16) * 2; | sc->reply_q_depth = ((sc->max_fw_cmds + 1 + 15) / 16 * 16) * 2; | ||||
sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * sc->max_fw_cmds; | sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * sc->max_fw_cmds; | ||||
sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth); | sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth); | ||||
sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + | sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + | ||||
(MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (sc->max_fw_cmds + 1)); | (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (sc->max_fw_cmds + 1)); | ||||
scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, | scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, | ||||
outbound_scratch_pad_2)); | outbound_scratch_pad_2)); | ||||
mrsas_dprint(sc, MRSAS_TRACE, "%s: sc->reply_q_depth 0x%x," | |||||
"sc->request_alloc_sz 0x%x, sc->reply_alloc_sz 0x%x," | |||||
"sc->io_frames_alloc_sz 0x%x\n", __func__, | |||||
sc->reply_q_depth, sc->request_alloc_sz, | |||||
sc->reply_alloc_sz, sc->io_frames_alloc_sz); | |||||
/* | /* | ||||
* If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set, | * If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set, | ||||
* Firmware support extended IO chain frame which is 4 time more | * Firmware support extended IO chain frame which is 4 time more | ||||
* than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) = | * than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) = | ||||
* 1K 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K | * 1K 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K | ||||
*/ | */ | ||||
if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK) | if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK) | ||||
sc->max_chain_frame_sz = | sc->max_chain_frame_sz = | ||||
((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5) | ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5) | ||||
* MEGASAS_1MB_IO; | * MEGASAS_1MB_IO; | ||||
else | else | ||||
sc->max_chain_frame_sz = | sc->max_chain_frame_sz = | ||||
((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5) | ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5) | ||||
* MEGASAS_256K_IO; | * MEGASAS_256K_IO; | ||||
sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * sc->max_fw_cmds; | sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * sc->max_fw_cmds; | ||||
sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - | sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - | ||||
offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16; | offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16; | ||||
sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION); | sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION); | ||||
sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2; | sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2; | ||||
mrsas_dprint(sc, MRSAS_INFO, | mrsas_dprint(sc, MRSAS_INFO, | ||||
"max sge: 0x%x, max chain frame size: 0x%x, " | "max sge: 0x%x, max chain frame size: 0x%x, " | ||||
"max fw cmd: 0x%x\n", sc->max_num_sge, | "max fw cmd: 0x%x sc->chain_frames_alloc_sz: 0x%x\n", | ||||
sc->max_chain_frame_sz, sc->max_fw_cmds); | sc->max_num_sge, | ||||
sc->max_chain_frame_sz, sc->max_fw_cmds, | |||||
sc->chain_frames_alloc_sz); | |||||
/* Used for pass thru MFI frame (DCMD) */ | /* Used for pass thru MFI frame (DCMD) */ | ||||
sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16; | sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16; | ||||
sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - | sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - | ||||
sizeof(MPI2_SGE_IO_UNION)) / 16; | sizeof(MPI2_SGE_IO_UNION)) / 16; | ||||
int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; | int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; | ||||
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines | scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, | ||||
outbound_scratch_pad_2)); | outbound_scratch_pad_2)); | ||||
sc->fw_sync_cache_support = (scratch_pad_2 & | sc->fw_sync_cache_support = (scratch_pad_2 & | ||||
MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0; | MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0; | ||||
} | } | ||||
IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024); | IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024); | ||||
IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT; | IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT; | ||||
IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER; | IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER; | ||||
IOCInitMsg->MsgVersion = MPI2_VERSION; | IOCInitMsg->MsgVersion = htole16(MPI2_VERSION); | ||||
IOCInitMsg->HeaderVersion = MPI2_HEADER_VERSION; | IOCInitMsg->HeaderVersion = htole16(MPI2_HEADER_VERSION); | ||||
IOCInitMsg->SystemRequestFrameSize = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4; | IOCInitMsg->SystemRequestFrameSize = htole16(MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4); | ||||
IOCInitMsg->ReplyDescriptorPostQueueDepth = sc->reply_q_depth; | IOCInitMsg->ReplyDescriptorPostQueueDepth = htole16(sc->reply_q_depth); | ||||
IOCInitMsg->ReplyDescriptorPostQueueAddress = sc->reply_desc_phys_addr; | IOCInitMsg->ReplyDescriptorPostQueueAddress = htole64(sc->reply_desc_phys_addr); | ||||
IOCInitMsg->SystemRequestFrameBaseAddress = sc->io_request_phys_addr; | IOCInitMsg->SystemRequestFrameBaseAddress = htole64(sc->io_request_phys_addr); | ||||
IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0); | IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0); | ||||
IOCInitMsg->HostPageSize = MR_DEFAULT_NVME_PAGE_SHIFT; | IOCInitMsg->HostPageSize = MR_DEFAULT_NVME_PAGE_SHIFT; | ||||
init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem; | init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem; | ||||
init_frame->cmd = MFI_CMD_INIT; | init_frame->cmd = MFI_CMD_INIT; | ||||
init_frame->cmd_status = 0xFF; | init_frame->cmd_status = 0xFF; | ||||
init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; | init_frame->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE); | ||||
/* driver support Extended MSIX */ | /* driver support Extended MSIX */ | ||||
if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) { | if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) { | ||||
init_frame->driver_operations. | init_frame->driver_operations. | ||||
mfi_capabilities.support_additional_msix = 1; | mfi_capabilities.support_additional_msix = 1; | ||||
} | } | ||||
if (sc->verbuf_mem) { | if (sc->verbuf_mem) { | ||||
snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n", | snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n", | ||||
MRSAS_VERSION); | MRSAS_VERSION); | ||||
init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr; | init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr; | ||||
init_frame->driver_ver_hi = 0; | init_frame->driver_ver_hi = 0; | ||||
} | } | ||||
init_frame->driver_operations.mfi_capabilities.support_ndrive_r1_lb = 1; | init_frame->driver_operations.mfi_capabilities.support_ndrive_r1_lb = 1; | ||||
init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1; | init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1; | ||||
init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1; | init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1; | ||||
if (sc->max_chain_frame_sz > MEGASAS_CHAIN_FRAME_SZ_MIN) | if (sc->max_chain_frame_sz > MEGASAS_CHAIN_FRAME_SZ_MIN) | ||||
init_frame->driver_operations.mfi_capabilities.support_ext_io_size = 1; | init_frame->driver_operations.mfi_capabilities.support_ext_io_size = 1; | ||||
init_frame->driver_operations.reg = htole32(init_frame->driver_operations.reg); | |||||
phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024; | phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024; | ||||
init_frame->queue_info_new_phys_addr_lo = phys_addr; | init_frame->queue_info_new_phys_addr_lo = htole32(phys_addr); | ||||
init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t); | init_frame->data_xfer_len = htole32(sizeof(Mpi2IOCInitRequest_t)); | ||||
req_desc.addr.Words = (bus_addr_t)sc->ioc_init_phys_mem; | req_desc.addr.u.low = htole32((bus_addr_t)sc->ioc_init_phys_mem & 0xFFFFFFFF); | ||||
req_desc.addr.u.high = htole32((bus_addr_t)sc->ioc_init_phys_mem >> 32); | |||||
req_desc.MFAIo.RequestFlags = | req_desc.MFAIo.RequestFlags = | ||||
(MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); | (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); | ||||
mrsas_disable_intr(sc); | mrsas_disable_intr(sc); | ||||
mrsas_dprint(sc, MRSAS_OCR, "Issuing IOC INIT command to FW.\n"); | mrsas_dprint(sc, MRSAS_OCR, "Issuing IOC INIT command to FW.\n"); | ||||
mrsas_write_64bit_req_desc(sc, req_desc.addr.u.low, req_desc.addr.u.high); | mrsas_write_64bit_req_desc(sc, req_desc.addr.u.low, req_desc.addr.u.high); | ||||
/* | /* | ||||
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines | |||||
* request descriptor address high | * request descriptor address high | ||||
*/ | */ | ||||
void | void | ||||
mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo, | mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo, | ||||
u_int32_t req_desc_hi) | u_int32_t req_desc_hi) | ||||
{ | { | ||||
mtx_lock(&sc->pci_lock); | mtx_lock(&sc->pci_lock); | ||||
mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port), | mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port), | ||||
req_desc_lo); | le32toh(req_desc_lo)); | ||||
mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port), | mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port), | ||||
req_desc_hi); | le32toh(req_desc_hi)); | ||||
mtx_unlock(&sc->pci_lock); | mtx_unlock(&sc->pci_lock); | ||||
} | } | ||||
/* | /* | ||||
* mrsas_fire_cmd: Sends command to FW | * mrsas_fire_cmd: Sends command to FW | ||||
* input: Adapter softstate | * input: Adapter softstate | ||||
* request descriptor address low | * request descriptor address low | ||||
* request descriptor address high | * request descriptor address high | ||||
* | * | ||||
* This functions fires the command to Firmware by writing to the | * This functions fires the command to Firmware by writing to the | ||||
* inbound_low_queue_port and inbound_high_queue_port. | * inbound_low_queue_port and inbound_high_queue_port. | ||||
*/ | */ | ||||
void | void | ||||
mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, | mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, | ||||
u_int32_t req_desc_hi) | u_int32_t req_desc_hi) | ||||
{ | { | ||||
if (sc->atomic_desc_support) | if (sc->atomic_desc_support) | ||||
mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_single_queue_port), | mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_single_queue_port), | ||||
req_desc_lo); | le32toh(req_desc_lo)); | ||||
else | else | ||||
mrsas_write_64bit_req_desc(sc, req_desc_lo, req_desc_hi); | mrsas_write_64bit_req_desc(sc, req_desc_lo, req_desc_hi); | ||||
} | } | ||||
/* | /* | ||||
* mrsas_transition_to_ready: Move FW to Ready state input: | * mrsas_transition_to_ready: Move FW to Ready state input: | ||||
* Adapter instance soft state | * Adapter instance soft state | ||||
* | * | ||||
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines | |||||
mrsas_ocr_thread(void *arg) | mrsas_ocr_thread(void *arg) | ||||
{ | { | ||||
struct mrsas_softc *sc; | struct mrsas_softc *sc; | ||||
u_int32_t fw_status, fw_state; | u_int32_t fw_status, fw_state; | ||||
u_int8_t tm_target_reset_failed = 0; | u_int8_t tm_target_reset_failed = 0; | ||||
sc = (struct mrsas_softc *)arg; | sc = (struct mrsas_softc *)arg; | ||||
mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__); | mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__); | ||||
Done Inline ActionsIs there any reason to remove this trace message? luporl: Is there any reason to remove this trace message? | |||||
sc->ocr_thread_active = 1; | sc->ocr_thread_active = 1; | ||||
mtx_lock(&sc->sim_lock); | mtx_lock(&sc->sim_lock); | ||||
for (;;) { | for (;;) { | ||||
/* Sleep for 1 second and check the queue status */ | /* Sleep for 1 second and check the queue status */ | ||||
msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, | msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, | ||||
"mrsas_ocr", sc->mrsas_fw_fault_check_delay * hz); | "mrsas_ocr", sc->mrsas_fw_fault_check_delay * hz); | ||||
if (sc->remove_in_progress || | if (sc->remove_in_progress || | ||||
sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) { | sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) { | ||||
▲ Show 20 Lines • Show All 522 Lines • ▼ Show 20 Lines | mrsas_get_ctrl_info(struct mrsas_softc *sc) | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = MFI_FRAME_DIR_READ; | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = sizeof(struct mrsas_ctrl_info); | dcmd->data_xfer_len = htole32(sizeof(struct mrsas_ctrl_info)); | ||||
dcmd->opcode = MR_DCMD_CTRL_GET_INFO; | dcmd->opcode = htole32(MR_DCMD_CTRL_GET_INFO); | ||||
dcmd->sgl.sge32[0].phys_addr = sc->ctlr_info_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32(sc->ctlr_info_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info); | dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_ctrl_info)); | ||||
if (!sc->mask_interrupts) | if (!sc->mask_interrupts) | ||||
retcode = mrsas_issue_blocked_cmd(sc, cmd); | retcode = mrsas_issue_blocked_cmd(sc, cmd); | ||||
else | else | ||||
retcode = mrsas_issue_polled(sc, cmd); | retcode = mrsas_issue_polled(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
goto dcmd_timeout; | goto dcmd_timeout; | ||||
else | else { | ||||
memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info)); | memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info)); | ||||
le32_to_cpus(&sc->ctrl_info->properties.OnOffProperties); | |||||
le32_to_cpus(&sc->ctrl_info->adapterOperations2); | |||||
le32_to_cpus(&sc->ctrl_info->adapterOperations3); | |||||
le16_to_cpus(&sc->ctrl_info->adapterOperations4); | |||||
} | |||||
do_ocr = 0; | do_ocr = 0; | ||||
mrsas_update_ext_vd_details(sc); | mrsas_update_ext_vd_details(sc); | ||||
sc->use_seqnum_jbod_fp = | sc->use_seqnum_jbod_fp = | ||||
sc->ctrl_info->adapterOperations3.useSeqNumJbodFP; | sc->ctrl_info->adapterOperations3.useSeqNumJbodFP; | ||||
sc->support_morethan256jbod = | sc->support_morethan256jbod = | ||||
sc->ctrl_info->adapterOperations4.supportPdMapTargetId; | sc->ctrl_info->adapterOperations4.supportPdMapTargetId; | ||||
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines | |||||
int | int | ||||
mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) | mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) | ||||
{ | { | ||||
struct mrsas_header *frame_hdr = &cmd->frame->hdr; | struct mrsas_header *frame_hdr = &cmd->frame->hdr; | ||||
u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; | u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; | ||||
int i, retcode = SUCCESS; | int i, retcode = SUCCESS; | ||||
frame_hdr->cmd_status = 0xFF; | frame_hdr->cmd_status = 0xFF; | ||||
frame_hdr->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; | frame_hdr->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE); | ||||
/* Issue the frame using inbound queue port */ | /* Issue the frame using inbound queue port */ | ||||
if (mrsas_issue_dcmd(sc, cmd)) { | if (mrsas_issue_dcmd(sc, cmd)) { | ||||
device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); | device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); | ||||
return (1); | return (1); | ||||
} | } | ||||
/* | /* | ||||
* Poll response timer to wait for Firmware response. While this | * Poll response timer to wait for Firmware response. While this | ||||
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines | mrsas_build_mpt_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) | ||||
req_desc = mrsas_get_request_desc(sc, index - 1); | req_desc = mrsas_get_request_desc(sc, index - 1); | ||||
if (!req_desc) | if (!req_desc) | ||||
return NULL; | return NULL; | ||||
req_desc->addr.Words = 0; | req_desc->addr.Words = 0; | ||||
req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); | req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); | ||||
req_desc->SCSIIO.SMID = index; | req_desc->SCSIIO.SMID = htole16(index); | ||||
return (req_desc); | return (req_desc); | ||||
} | } | ||||
/* | /* | ||||
* mrsas_build_mptmfi_passthru: Builds a MPT MFI Passthru command | * mrsas_build_mptmfi_passthru: Builds a MPT MFI Passthru command | ||||
* input: Adapter soft state mfi cmd pointer | * input: Adapter soft state mfi cmd pointer | ||||
* | * | ||||
Show All 18 Lines | mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *mfi_cmd) | ||||
mpt_cmd->sync_cmd_idx = mfi_cmd->index; | mpt_cmd->sync_cmd_idx = mfi_cmd->index; | ||||
/* | /* | ||||
* For cmds where the flag is set, store the flag and check on | * For cmds where the flag is set, store the flag and check on | ||||
* completion. For cmds with this flag, don't call | * completion. For cmds with this flag, don't call | ||||
* mrsas_complete_cmd. | * mrsas_complete_cmd. | ||||
*/ | */ | ||||
if (frame_hdr->flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE) | if (frame_hdr->flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)) | ||||
mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; | mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; | ||||
io_req = mpt_cmd->io_request; | io_req = mpt_cmd->io_request; | ||||
if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) { | if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) { | ||||
pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL; | pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL; | ||||
sgl_ptr_end += sc->max_sge_in_main_msg - 1; | sgl_ptr_end += sc->max_sge_in_main_msg - 1; | ||||
sgl_ptr_end->Flags = 0; | sgl_ptr_end->Flags = 0; | ||||
} | } | ||||
mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain; | mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain; | ||||
io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST; | io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST; | ||||
io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4; | io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4; | ||||
io_req->ChainOffset = sc->chain_offset_mfi_pthru; | io_req->ChainOffset = sc->chain_offset_mfi_pthru; | ||||
mpi25_ieee_chain->Address = mfi_cmd->frame_phys_addr; | mpi25_ieee_chain->Address = htole64(mfi_cmd->frame_phys_addr); | ||||
mpi25_ieee_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT | | mpi25_ieee_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT | | ||||
MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; | MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; | ||||
mpi25_ieee_chain->Length = sc->max_chain_frame_sz; | mpi25_ieee_chain->Length = htole32(sc->max_chain_frame_sz); | ||||
return (0); | return (0); | ||||
} | } | ||||
/* | /* | ||||
* mrsas_issue_blocked_cmd: Synchronous wrapper around regular FW cmds | * mrsas_issue_blocked_cmd: Synchronous wrapper around regular FW cmds | ||||
* input: Adapter soft state Command to be issued | * input: Adapter soft state Command to be issued | ||||
* | * | ||||
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines | if ((cmd->frame->dcmd.opcode == | ||||
sc->use_seqnum_jbod_fp = 0; | sc->use_seqnum_jbod_fp = 0; | ||||
device_printf(sc->mrsas_dev, | device_printf(sc->mrsas_dev, | ||||
"Jbod map sync failed, status=%x\n", cmd_status); | "Jbod map sync failed, status=%x\n", cmd_status); | ||||
} | } | ||||
mtx_unlock(&sc->raidmap_lock); | mtx_unlock(&sc->raidmap_lock); | ||||
break; | break; | ||||
} | } | ||||
/* See if got an event notification */ | /* See if got an event notification */ | ||||
if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_WAIT) | if (le32toh(cmd->frame->dcmd.opcode) == MR_DCMD_CTRL_EVENT_WAIT) | ||||
mrsas_complete_aen(sc, cmd); | mrsas_complete_aen(sc, cmd); | ||||
else | else | ||||
mrsas_wakeup(sc, cmd); | mrsas_wakeup(sc, cmd); | ||||
break; | break; | ||||
case MFI_CMD_ABORT: | case MFI_CMD_ABORT: | ||||
/* Command issued to abort another cmd return */ | /* Command issued to abort another cmd return */ | ||||
mrsas_complete_abort(sc, cmd); | mrsas_complete_abort(sc, cmd); | ||||
break; | break; | ||||
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines | megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend) | ||||
} | } | ||||
memset(pd_sync, 0, pd_seq_map_sz); | memset(pd_sync, 0, pd_seq_map_sz); | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = (pd_seq_map_sz); | dcmd->data_xfer_len = htole32(pd_seq_map_sz); | ||||
dcmd->opcode = (MR_DCMD_SYSTEM_PD_MAP_GET_INFO); | dcmd->opcode = htole32(MR_DCMD_SYSTEM_PD_MAP_GET_INFO); | ||||
dcmd->sgl.sge32[0].phys_addr = (pd_seq_h); | dcmd->sgl.sge32[0].phys_addr = htole32(pd_seq_h & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = (pd_seq_map_sz); | dcmd->sgl.sge32[0].length = htole32(pd_seq_map_sz); | ||||
if (pend) { | if (pend) { | ||||
dcmd->mbox.b[0] = MRSAS_DCMD_MBOX_PEND_FLAG; | dcmd->mbox.b[0] = MRSAS_DCMD_MBOX_PEND_FLAG; | ||||
dcmd->flags = (MFI_FRAME_DIR_WRITE); | dcmd->flags = htole16(MFI_FRAME_DIR_WRITE); | ||||
sc->jbod_seq_cmd = cmd; | sc->jbod_seq_cmd = cmd; | ||||
if (mrsas_issue_dcmd(sc, cmd)) { | if (mrsas_issue_dcmd(sc, cmd)) { | ||||
device_printf(sc->mrsas_dev, | device_printf(sc->mrsas_dev, | ||||
"Fail to send sync map info command.\n"); | "Fail to send sync map info command.\n"); | ||||
return 1; | return 1; | ||||
} else | } else | ||||
return 0; | return 0; | ||||
} else | } else | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = htole16(MFI_FRAME_DIR_READ); | ||||
retcode = mrsas_issue_polled(sc, cmd); | retcode = mrsas_issue_polled(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
goto dcmd_timeout; | goto dcmd_timeout; | ||||
if (pd_sync->count > MAX_PHYSICAL_DEVICES) { | if (le32toh(pd_sync->count) > MAX_PHYSICAL_DEVICES) { | ||||
device_printf(sc->mrsas_dev, | device_printf(sc->mrsas_dev, | ||||
"driver supports max %d JBOD, but FW reports %d\n", | "driver supports max %d JBOD, but FW reports %d\n", | ||||
MAX_PHYSICAL_DEVICES, pd_sync->count); | MAX_PHYSICAL_DEVICES, pd_sync->count); | ||||
retcode = -EINVAL; | retcode = -EINVAL; | ||||
} | } | ||||
if (!retcode) | if (!retcode) | ||||
sc->pd_seq_map_id++; | sc->pd_seq_map_id++; | ||||
do_ocr = 0; | do_ocr = 0; | ||||
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines | if (!map) { | ||||
return (ENOMEM); | return (ENOMEM); | ||||
} | } | ||||
memset(map, 0, sizeof(sc->max_map_sz)); | memset(map, 0, sizeof(sc->max_map_sz)); | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = htole16(MFI_FRAME_DIR_READ); | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = sc->current_map_sz; | dcmd->data_xfer_len = htole32(sc->current_map_sz); | ||||
dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO; | dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO); | ||||
dcmd->sgl.sge32[0].phys_addr = map_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = sc->current_map_sz; | dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz); | ||||
retcode = mrsas_issue_polled(sc, cmd); | retcode = mrsas_issue_polled(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; | sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; | ||||
return (retcode); | return (retcode); | ||||
} | } | ||||
Show All 40 Lines | for (i = 0; i < num_lds; i++, ld_sync++) { | ||||
raid = MR_LdRaidGet(i, map); | raid = MR_LdRaidGet(i, map); | ||||
ld_sync->targetId = MR_GetLDTgtId(i, map); | ld_sync->targetId = MR_GetLDTgtId(i, map); | ||||
ld_sync->seqNum = raid->seqNum; | ld_sync->seqNum = raid->seqNum; | ||||
} | } | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_WRITE; | dcmd->flags = htole16(MFI_FRAME_DIR_WRITE); | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = sc->current_map_sz; | dcmd->data_xfer_len = htole32(sc->current_map_sz); | ||||
dcmd->mbox.b[0] = num_lds; | dcmd->mbox.b[0] = num_lds; | ||||
dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG; | dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG; | ||||
dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO; | dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO); | ||||
dcmd->sgl.sge32[0].phys_addr = map_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = sc->current_map_sz; | dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz); | ||||
sc->map_update_cmd = cmd; | sc->map_update_cmd = cmd; | ||||
if (mrsas_issue_dcmd(sc, cmd)) { | if (mrsas_issue_dcmd(sc, cmd)) { | ||||
device_printf(sc->mrsas_dev, | device_printf(sc->mrsas_dev, | ||||
"Fail to send sync map info command.\n"); | "Fail to send sync map info command.\n"); | ||||
return (1); | return (1); | ||||
} | } | ||||
return (retcode); | return (retcode); | ||||
Show All 20 Lines | device_printf(sc->mrsas_dev, | ||||
"Cannot alloc for get PD info cmd\n"); | "Cannot alloc for get PD info cmd\n"); | ||||
return; | return; | ||||
} | } | ||||
dcmd = &cmd->frame->dcmd; | dcmd = &cmd->frame->dcmd; | ||||
memset(sc->pd_info_mem, 0, sizeof(struct mrsas_pd_info)); | memset(sc->pd_info_mem, 0, sizeof(struct mrsas_pd_info)); | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->mbox.s[0] = device_id; | dcmd->mbox.s[0] = htole16(device_id); | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = MFI_FRAME_DIR_READ; | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = sizeof(struct mrsas_pd_info); | dcmd->data_xfer_len = htole32(sizeof(struct mrsas_pd_info)); | ||||
dcmd->opcode = MR_DCMD_PD_GET_INFO; | dcmd->opcode = htole32(MR_DCMD_PD_GET_INFO); | ||||
dcmd->sgl.sge32[0].phys_addr = (u_int32_t)sc->pd_info_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->pd_info_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = sizeof(struct mrsas_pd_info); | dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_pd_info)); | ||||
if (!sc->mask_interrupts) | if (!sc->mask_interrupts) | ||||
retcode = mrsas_issue_blocked_cmd(sc, cmd); | retcode = mrsas_issue_blocked_cmd(sc, cmd); | ||||
else | else | ||||
retcode = mrsas_issue_polled(sc, cmd); | retcode = mrsas_issue_polled(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
goto dcmd_timeout; | goto dcmd_timeout; | ||||
sc->target_list[device_id].interface_type = | sc->target_list[device_id].interface_type = | ||||
sc->pd_info_mem->state.ddf.pdType.intf; | le16toh(sc->pd_info_mem->state.ddf.pdType.intf); | ||||
do_ocr = 0; | do_ocr = 0; | ||||
dcmd_timeout: | dcmd_timeout: | ||||
if (do_ocr) | if (do_ocr) | ||||
sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; | sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; | ||||
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines | mrsas_get_pd_list(struct mrsas_softc *sc) | ||||
int retcode = 0, pd_index = 0, pd_count = 0, pd_list_size; | int retcode = 0, pd_index = 0, pd_count = 0, pd_list_size; | ||||
u_int8_t do_ocr = 1; | u_int8_t do_ocr = 1; | ||||
struct mrsas_mfi_cmd *cmd; | struct mrsas_mfi_cmd *cmd; | ||||
struct mrsas_dcmd_frame *dcmd; | struct mrsas_dcmd_frame *dcmd; | ||||
struct MR_PD_LIST *pd_list_mem; | struct MR_PD_LIST *pd_list_mem; | ||||
struct MR_PD_ADDRESS *pd_addr; | struct MR_PD_ADDRESS *pd_addr; | ||||
bus_addr_t pd_list_phys_addr = 0; | bus_addr_t pd_list_phys_addr = 0; | ||||
struct mrsas_tmp_dcmd *tcmd; | struct mrsas_tmp_dcmd *tcmd; | ||||
u_int16_t dev_id; | |||||
cmd = mrsas_get_mfi_cmd(sc); | cmd = mrsas_get_mfi_cmd(sc); | ||||
if (!cmd) { | if (!cmd) { | ||||
device_printf(sc->mrsas_dev, | device_printf(sc->mrsas_dev, | ||||
"Cannot alloc for get PD list cmd\n"); | "Cannot alloc for get PD list cmd\n"); | ||||
return 1; | return 1; | ||||
} | } | ||||
dcmd = &cmd->frame->dcmd; | dcmd = &cmd->frame->dcmd; | ||||
Show All 13 Lines | mrsas_get_pd_list(struct mrsas_softc *sc) | ||||
} | } | ||||
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); | ||||
dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST; | dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST; | ||||
dcmd->mbox.b[1] = 0; | dcmd->mbox.b[1] = 0; | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = htole16(MFI_FRAME_DIR_READ); | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
dcmd->data_xfer_len = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); | dcmd->data_xfer_len = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST)); | ||||
dcmd->opcode = MR_DCMD_PD_LIST_QUERY; | dcmd->opcode = htole32(MR_DCMD_PD_LIST_QUERY); | ||||
dcmd->sgl.sge32[0].phys_addr = pd_list_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32(pd_list_phys_addr & 0xFFFFFFFF); | ||||
dcmd->sgl.sge32[0].length = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); | dcmd->sgl.sge32[0].length = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST)); | ||||
if (!sc->mask_interrupts) | if (!sc->mask_interrupts) | ||||
retcode = mrsas_issue_blocked_cmd(sc, cmd); | retcode = mrsas_issue_blocked_cmd(sc, cmd); | ||||
else | else | ||||
retcode = mrsas_issue_polled(sc, cmd); | retcode = mrsas_issue_polled(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
goto dcmd_timeout; | goto dcmd_timeout; | ||||
/* Get the instance PD list */ | /* Get the instance PD list */ | ||||
pd_count = MRSAS_MAX_PD; | pd_count = MRSAS_MAX_PD; | ||||
pd_addr = pd_list_mem->addr; | pd_addr = pd_list_mem->addr; | ||||
if (pd_list_mem->count < pd_count) { | if (le32toh(pd_list_mem->count) < pd_count) { | ||||
memset(sc->local_pd_list, 0, | memset(sc->local_pd_list, 0, | ||||
MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); | MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); | ||||
for (pd_index = 0; pd_index < pd_list_mem->count; pd_index++) { | for (pd_index = 0; pd_index < le32toh(pd_list_mem->count); pd_index++) { | ||||
sc->local_pd_list[pd_addr->deviceId].tid = pd_addr->deviceId; | dev_id = le16toh(pd_addr->deviceId); | ||||
sc->local_pd_list[pd_addr->deviceId].driveType = | sc->local_pd_list[dev_id].tid = dev_id; | ||||
pd_addr->scsiDevType; | sc->local_pd_list[dev_id].driveType = | ||||
sc->local_pd_list[pd_addr->deviceId].driveState = | le16toh(pd_addr->scsiDevType); | ||||
sc->local_pd_list[dev_id].driveState = | |||||
MR_PD_STATE_SYSTEM; | MR_PD_STATE_SYSTEM; | ||||
if (sc->target_list[pd_addr->deviceId].target_id == 0xffff) | if (sc->target_list[dev_id].target_id == 0xffff) | ||||
mrsas_add_target(sc, pd_addr->deviceId); | mrsas_add_target(sc, dev_id); | ||||
pd_addr++; | pd_addr++; | ||||
Done Inline ActionsIt would be nice to save le16toh(pd_addr->deviceId) to a temporary variable and use it instead of repeating the le16toh() calls. luporl: It would be nice to save le16toh(pd_addr->deviceId) to a temporary variable and use it instead… | |||||
} | } | ||||
for (pd_index = 0; pd_index < MRSAS_MAX_PD; pd_index++) { | for (pd_index = 0; pd_index < MRSAS_MAX_PD; pd_index++) { | ||||
if ((sc->local_pd_list[pd_index].driveState != | if ((sc->local_pd_list[pd_index].driveState != | ||||
MR_PD_STATE_SYSTEM) && | MR_PD_STATE_SYSTEM) && | ||||
(sc->target_list[pd_index].target_id != | (sc->target_list[pd_index].target_id != | ||||
0xffff)) { | 0xffff)) { | ||||
mrsas_remove_target(sc, pd_index); | mrsas_remove_target(sc, pd_index); | ||||
} | } | ||||
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines | mrsas_get_ld_list(struct mrsas_softc *sc) | ||||
if (sc->max256vdSupport) | if (sc->max256vdSupport) | ||||
dcmd->mbox.b[0] = 1; | dcmd->mbox.b[0] = 1; | ||||
dcmd->cmd = MFI_CMD_DCMD; | dcmd->cmd = MFI_CMD_DCMD; | ||||
dcmd->cmd_status = 0xFF; | dcmd->cmd_status = 0xFF; | ||||
dcmd->sge_count = 1; | dcmd->sge_count = 1; | ||||
dcmd->flags = MFI_FRAME_DIR_READ; | dcmd->flags = MFI_FRAME_DIR_READ; | ||||
dcmd->timeout = 0; | dcmd->timeout = 0; | ||||
dcmd->data_xfer_len = sizeof(struct MR_LD_LIST); | dcmd->data_xfer_len = htole32(sizeof(struct MR_LD_LIST)); | ||||
dcmd->opcode = MR_DCMD_LD_GET_LIST; | dcmd->opcode = htole32(MR_DCMD_LD_GET_LIST); | ||||
dcmd->sgl.sge32[0].phys_addr = ld_list_phys_addr; | dcmd->sgl.sge32[0].phys_addr = htole32(ld_list_phys_addr); | ||||
dcmd->sgl.sge32[0].length = sizeof(struct MR_LD_LIST); | dcmd->sgl.sge32[0].length = htole32(sizeof(struct MR_LD_LIST)); | ||||
dcmd->pad_0 = 0; | dcmd->pad_0 = 0; | ||||
if (!sc->mask_interrupts) | if (!sc->mask_interrupts) | ||||
retcode = mrsas_issue_blocked_cmd(sc, cmd); | retcode = mrsas_issue_blocked_cmd(sc, cmd); | ||||
else | else | ||||
retcode = mrsas_issue_polled(sc, cmd); | retcode = mrsas_issue_polled(sc, cmd); | ||||
if (retcode == ETIMEDOUT) | if (retcode == ETIMEDOUT) | ||||
goto dcmd_timeout; | goto dcmd_timeout; | ||||
#if VD_EXT_DEBUG | #if VD_EXT_DEBUG | ||||
printf("Number of LDs %d\n", ld_list_mem->ldCount); | printf("Number of LDs %d\n", ld_list_mem->ldCount); | ||||
#endif | #endif | ||||
/* Get the instance LD list */ | /* Get the instance LD list */ | ||||
if (ld_list_mem->ldCount <= sc->fw_supported_vd_count) { | if (le32toh(ld_list_mem->ldCount) <= sc->fw_supported_vd_count) { | ||||
sc->CurLdCount = ld_list_mem->ldCount; | sc->CurLdCount = le32toh(ld_list_mem->ldCount); | ||||
memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT); | memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT); | ||||
for (ld_index = 0; ld_index < ld_list_mem->ldCount; ld_index++) { | for (ld_index = 0; ld_index < le32toh(ld_list_mem->ldCount); ld_index++) { | ||||
ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; | ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; | ||||
drv_tgt_id = ids + MRSAS_MAX_PD; | drv_tgt_id = ids + MRSAS_MAX_PD; | ||||
if (ld_list_mem->ldList[ld_index].state != 0) { | if (ld_list_mem->ldList[ld_index].state != 0) { | ||||
sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; | sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; | ||||
if (sc->target_list[drv_tgt_id].target_id == | if (sc->target_list[drv_tgt_id].target_id == | ||||
0xffff) | 0xffff) | ||||
mrsas_add_target(sc, drv_tgt_id); | mrsas_add_target(sc, drv_tgt_id); | ||||
} else { | } else { | ||||
▲ Show 20 Lines • Show All 324 Lines • Show Last 20 Lines |
Why was this check removed?