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sys/arm64/include/armreg.h
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#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) | #define ISS_DATA_DFSC_ECC_L0 (0x1c << 0) | ||||
#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) | #define ISS_DATA_DFSC_ECC_L1 (0x1d << 0) | ||||
#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) | #define ISS_DATA_DFSC_ECC_L2 (0x1e << 0) | ||||
#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) | #define ISS_DATA_DFSC_ECC_L3 (0x1f << 0) | ||||
#define ISS_DATA_DFSC_ALIGN (0x21 << 0) | #define ISS_DATA_DFSC_ALIGN (0x21 << 0) | ||||
#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) | #define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0) | ||||
#define ESR_ELx_IL (0x01 << 25) | #define ESR_ELx_IL (0x01 << 25) | ||||
#define ESR_ELx_EC_SHIFT 26 | #define ESR_ELx_EC_SHIFT 26 | ||||
#define ESR_ELx_EC_MASK (0x3f << 26) | #define ESR_ELx_EC_MASK (0x3f << ESR_ELx_EC_SHIFT) | ||||
#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) | #define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) | ||||
#define EXCP_UNKNOWN 0x00 /* Unkwn exception */ | #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ | ||||
#define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ | #define EXCP_TRAP_WFI_WFE 0x01 /* Trapped WFI or WFE */ | ||||
#define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ | #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ | ||||
#define EXCP_ILL_STATE 0x0e /* Illegal execution state */ | #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ | ||||
#define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ | #define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ | ||||
#define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ | #define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ | ||||
#define EXCP_HVC 0x16 /* HVC trap */ | #define EXCP_HVC 0x16 /* HVC trap */ | ||||
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