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sys/dev/pci/pcivar.h
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* | * | ||||
* $FreeBSD$ | * $FreeBSD$ | ||||
* | * | ||||
*/ | */ | ||||
#ifndef _PCIVAR_H_ | #ifndef _PCIVAR_H_ | ||||
#define _PCIVAR_H_ | #define _PCIVAR_H_ | ||||
#include <sys/systm.h> | |||||
#include <sys/lock.h> | |||||
#include <sys/mutex.h> | |||||
#include <sys/queue.h> | #include <sys/queue.h> | ||||
#include <sys/taskqueue.h> | |||||
/* some PCI bus constants */ | /* some PCI bus constants */ | ||||
#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ | #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ | ||||
#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ | #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ | ||||
#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ | #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ | ||||
typedef uint64_t pci_addr_t; | typedef uint64_t pci_addr_t; | ||||
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/* Interesting values for HyperTransport */ | /* Interesting values for HyperTransport */ | ||||
struct pcicfg_ht { | struct pcicfg_ht { | ||||
uint8_t ht_slave; /* Non-zero if device is an HT slave. */ | uint8_t ht_slave; /* Non-zero if device is an HT slave. */ | ||||
uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ | uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ | ||||
uint16_t ht_msictrl; /* MSI mapping control */ | uint16_t ht_msictrl; /* MSI mapping control */ | ||||
uint64_t ht_msiaddr; /* MSI mapping base address */ | uint64_t ht_msiaddr; /* MSI mapping base address */ | ||||
}; | }; | ||||
#define PCIE_MSI_MESSAGES 2 | |||||
/* Interesting values for PCI-express */ | /* Interesting values for PCI-express */ | ||||
struct pcicfg_pcie { | struct pcicfg_pcie { | ||||
uint8_t pcie_location; /* Offset of PCI-e capability registers. */ | uint8_t pcie_location; /* Offset of PCI-e capability registers. */ | ||||
uint8_t pcie_type; /* Device type. */ | uint8_t pcie_type; /* Device type. */ | ||||
uint16_t pcie_flags; /* Device capabilities register. */ | uint16_t pcie_flags; /* Device capabilities register. */ | ||||
uint16_t pcie_device_ctl; /* Device control register. */ | uint16_t pcie_device_ctl; /* Device control register. */ | ||||
uint16_t pcie_link_ctl; /* Link control register. */ | uint16_t pcie_link_ctl; /* Link control register. */ | ||||
uint16_t pcie_slot_ctl; /* Slot control register. */ | uint16_t pcie_slot_ctl; /* Slot control register. */ | ||||
uint16_t pcie_root_ctl; /* Root control register. */ | uint16_t pcie_root_ctl; /* Root control register. */ | ||||
uint16_t pcie_device_ctl2; /* Second device control register. */ | uint16_t pcie_device_ctl2; /* Second device control register. */ | ||||
uint16_t pcie_link_ctl2; /* Second link control register. */ | uint16_t pcie_link_ctl2; /* Second link control register. */ | ||||
uint16_t pcie_slot_ctl2; /* Second slot control register. */ | uint16_t pcie_slot_ctl2; /* Second slot control register. */ | ||||
struct resource_spec *pcie_irq_spec; | |||||
struct resource *pcie_res_irq[PCIE_MSI_MESSAGES]; | |||||
void *pcie_intrhand[PCIE_MSI_MESSAGES]; | |||||
}; | }; | ||||
jhb: Is the idea of putting these here rather than in pcicfg_hp because the same message can be… | |||||
struct pcicfg_pcix { | struct pcicfg_pcix { | ||||
uint16_t pcix_command; | uint16_t pcix_command; | ||||
uint8_t pcix_location; /* Offset of PCI-X capability registers. */ | uint8_t pcix_location; /* Offset of PCI-X capability registers. */ | ||||
}; | }; | ||||
struct pcicfg_vf { | struct pcicfg_vf { | ||||
int index; | int index; | ||||
}; | }; | ||||
/* Interesting values for PCIe Hotplug */ | |||||
struct pcicfg_hp { | |||||
struct task hp_inttask; | |||||
struct callout hp_co; | |||||
int hp_cnt; /* Giant locked */ | |||||
uint32_t hp_slotcap; /* cache this */ | |||||
}; | |||||
#define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ | #define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ | ||||
/* config header information common to all header types */ | /* config header information common to all header types */ | ||||
typedef struct pcicfg { | typedef struct pcicfg { | ||||
struct device *dev; /* device which owns this */ | struct device *dev; /* device which owns this */ | ||||
STAILQ_HEAD(, pci_map) maps; /* BARs */ | STAILQ_HEAD(, pci_map) maps; /* BARs */ | ||||
Show All 35 Lines | typedef struct pcicfg { | ||||
struct pcicfg_vpd vpd; /* Vital product data */ | struct pcicfg_vpd vpd; /* Vital product data */ | ||||
struct pcicfg_msi msi; /* PCI MSI */ | struct pcicfg_msi msi; /* PCI MSI */ | ||||
struct pcicfg_msix msix; /* PCI MSI-X */ | struct pcicfg_msix msix; /* PCI MSI-X */ | ||||
struct pcicfg_ht ht; /* HyperTransport */ | struct pcicfg_ht ht; /* HyperTransport */ | ||||
struct pcicfg_pcie pcie; /* PCI Express */ | struct pcicfg_pcie pcie; /* PCI Express */ | ||||
struct pcicfg_pcix pcix; /* PCI-X */ | struct pcicfg_pcix pcix; /* PCI-X */ | ||||
struct pcicfg_iov *iov; /* SR-IOV */ | struct pcicfg_iov *iov; /* SR-IOV */ | ||||
struct pcicfg_vf vf; /* SR-IOV Virtual Function */ | struct pcicfg_vf vf; /* SR-IOV Virtual Function */ | ||||
struct pcicfg_hp hp; /* Hotplug */ | |||||
} pcicfgregs; | } pcicfgregs; | ||||
/* additional type 1 device config header information (PCI to PCI bridge) */ | /* additional type 1 device config header information (PCI to PCI bridge) */ | ||||
#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) | #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) | ||||
#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) | #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) | ||||
#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) | #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) | ||||
#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) | #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) | ||||
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Is the idea of putting these here rather than in pcicfg_hp because the same message can be overloaded for both hotplug and other things like AER?