Differential D26976 Diff 78821 sys/dts/arm64/foundation-v8.dtsi

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sys/dts/arm64/foundation-v8.dtsi

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				/*
				* ARM Ltd.
				*
				* ARMv8 Foundation model DTS
				*/

				/ {
				model = "Foundation-v8A";
				compatible = "arm,foundation-aarch64", "arm,vexpress";
				interrupt-parent = <&gic>;
				#address-cells = <2>;
				#size-cells = <2>;

				chosen { };

				aliases {
				serial0 = &v2m_serial0;
				serial1 = &v2m_serial1;
				serial2 = &v2m_serial2;
				serial3 = &v2m_serial3;
				};

				cpus {
				#address-cells = <2>;
				#size-cells = <0>;

				cpu@0 {
				device_type = "cpu";
				compatible = "arm,armv8";
				reg = <0x0 0x0>;
				next-level-cache = <&L2_0>;
				};

				L2_0: l2-cache0 {
				compatible = "cache";
				};
				};

				memory@80000000 {
				device_type = "memory";
				reg = <0x00000000 0x80000000 0 0x80000000>,
				<0x00000008 0x80000000 0 0x80000000>;
				};

				timer {
				compatible = "arm,armv8-timer";
				interrupts = <1 13 0xf08>,
				<1 14 0xf08>,
				<1 11 0xf08>,
				<1 10 0xf08>;
				clock-frequency = <100000000>;
				};

				pmu {
				compatible = "arm,armv8-pmuv3";
				interrupts = <0 60 4>,
				<0 61 4>,
				<0 62 4>,
				<0 63 4>;
				};

				watchdog@2a440000 {
				compatible = "arm,sbsa-gwdt";
				reg = <0x0 0x2a440000 0 0x1000>,
				<0x0 0x2a450000 0 0x1000>;
				interrupts = <0 27 4>;
				timeout-sec = <30>;
				};

				smb@08000000 {
				compatible = "arm,vexpress,v2m-p1", "simple-bus";
				arm,v2m-memory-map = "rs1";
				#address-cells = <2>; /* SMB chipselect number and offset */
				#size-cells = <1>;

				ranges = <0 0 0 0x08000000 0x04000000>,
				<1 0 0 0x14000000 0x04000000>,
				<2 0 0 0x18000000 0x04000000>,
				<3 0 0 0x1c000000 0x04000000>,
				<4 0 0 0x0c000000 0x04000000>,
				<5 0 0 0x10000000 0x04000000>;

				#interrupt-cells = <3>;

				ethernet@2,02000000 {
				compatible = "smsc,lan91c111";
				reg = <2 0x02000000 0x10000>;
				interrupts = <0 15 4>;
				};

				v2m_clk24mhz: clk24mhz {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <24000000>;
				clock-output-names = "v2m:clk24mhz";
				};

				v2m_refclk1mhz: refclk1mhz {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <1000000>;
				clock-output-names = "v2m:refclk1mhz";
				};

				v2m_refclk32khz: refclk32khz {
				compatible = "fixed-clock";
				#clock-cells = <0>;
				clock-frequency = <32768>;
				clock-output-names = "v2m:refclk32khz";
				};

				iofpga@3,00000000 {
				compatible = "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 3 0 0x200000>;

				v2m_sysreg: sysreg@010000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
				};

				v2m_serial0: uart@090000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <0 5 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial1: uart@0a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <0 6 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial2: uart@0b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <0 7 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
				};

				v2m_serial3: uart@0c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <0 8 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
				};

				virtio_block@0130000 {
				compatible = "virtio,mmio";
				reg = <0x130000 0x200>;
				interrupts = <0 42 4>;
				};
				};
				};
				};