Differential D25793 Diff 76948 sys/dev/axgbe/xgbe-common.h

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sys/dev/axgbe/xgbe-common.h

/*		/*
* AMD 10Gb Ethernet driver		* AMD 10Gb Ethernet driver
*		*
		* Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
		rgrimesUnsubmitted Done Inline Actions This should probably have dates updated to 2014-2016, 2020. rgrimes: This should probably have dates updated to 2014-2016, 2020.
		rajesh1.kumar_amd.comAuthorUnsubmitted Done Inline Actions Other places also modified as needed. rajesh1.kumar_amd.com: Other places also modified as needed.
		*
* This file is available to you under your choice of the following two		* This file is available to you under your choice of the following two
* licenses:		* licenses:
*		*
* License 1: GPLv2		* License 1: GPLv2
*		*
* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
*
* This file is free software; you may copy, redistribute and/or modify		* This file is free software; you may copy, redistribute and/or modify
* it under the terms of the GNU General Public License as published by		* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or (at		* the Free Software Foundation, either version 2 of the License, or (at
* your option) any later version.		* your option) any later version.
*		*
* This file is distributed in the hope that it will be useful, but		* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of		* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS		* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN		* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)		* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF		* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.		* THE POSSIBILITY OF SUCH DAMAGE.
*		*
*		*
* License 2: Modified BSD		* License 2: Modified BSD
*		*
* Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without		* Redistribution and use in source and binary forms, with or without
		rgrimesUnsubmitted Done Inline Actions Technically a copyright and license are 2 separate and different things, the "Copyright" should be factored out of the license section and placed before it. rgrimes: Technically a copyright and license are 2 separate and different things, the "Copyright" should…
		rajesh1.kumar_amd.comAuthorUnsubmitted Done Inline Actions Moved copyright above the License text and just have one instance. rajesh1.kumar_amd.com: Moved copyright above the License text and just have one instance.
* modification, are permitted provided that the following conditions are met:		* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright		* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.		* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright		* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the		* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.		* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the		* * Neither the name of Advanced Micro Devices, Inc. nor the
* names of its contributors may be used to endorse or promote products		* names of its contributors may be used to endorse or promote products
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#include <sys/rman.h>		#include <sys/rman.h>

/* DMA register offsets */		/* DMA register offsets */
#define DMA_MR 0x3000		#define DMA_MR 0x3000
#define DMA_SBMR 0x3004		#define DMA_SBMR 0x3004
#define DMA_ISR 0x3008		#define DMA_ISR 0x3008
#define DMA_AXIARCR 0x3010		#define DMA_AXIARCR 0x3010
#define DMA_AXIAWCR 0x3018		#define DMA_AXIAWCR 0x3018
		#define DMA_AXIAWARCR 0x301c
#define DMA_DSR0 0x3020		#define DMA_DSR0 0x3020
#define DMA_DSR1 0x3024		#define DMA_DSR1 0x3024
		#define DMA_DSR2 0x3028
		#define DMA_DSR3 0x302C
		#define DMA_DSR4 0x3030
		#define DMA_TXEDMACR 0x3040
		#define DMA_RXEDMACR 0x3044

/* DMA register entry bit positions and sizes */		/* DMA register entry bit positions and sizes */
#define DMA_AXIARCR_DRC_INDEX 0
#define DMA_AXIARCR_DRC_WIDTH 4
#define DMA_AXIARCR_DRD_INDEX 4
#define DMA_AXIARCR_DRD_WIDTH 2
#define DMA_AXIARCR_TEC_INDEX 8
#define DMA_AXIARCR_TEC_WIDTH 4
#define DMA_AXIARCR_TED_INDEX 12
#define DMA_AXIARCR_TED_WIDTH 2
#define DMA_AXIARCR_THC_INDEX 16
#define DMA_AXIARCR_THC_WIDTH 4
#define DMA_AXIARCR_THD_INDEX 20
#define DMA_AXIARCR_THD_WIDTH 2
#define DMA_AXIAWCR_DWC_INDEX 0
#define DMA_AXIAWCR_DWC_WIDTH 4
#define DMA_AXIAWCR_DWD_INDEX 4
#define DMA_AXIAWCR_DWD_WIDTH 2
#define DMA_AXIAWCR_RPC_INDEX 8
#define DMA_AXIAWCR_RPC_WIDTH 4
#define DMA_AXIAWCR_RPD_INDEX 12
#define DMA_AXIAWCR_RPD_WIDTH 2
#define DMA_AXIAWCR_RHC_INDEX 16
#define DMA_AXIAWCR_RHC_WIDTH 4
#define DMA_AXIAWCR_RHD_INDEX 20
#define DMA_AXIAWCR_RHD_WIDTH 2
#define DMA_AXIAWCR_TDC_INDEX 24
#define DMA_AXIAWCR_TDC_WIDTH 4
#define DMA_AXIAWCR_TDD_INDEX 28
#define DMA_AXIAWCR_TDD_WIDTH 2
#define DMA_ISR_MACIS_INDEX 17		#define DMA_ISR_MACIS_INDEX 17
#define DMA_ISR_MACIS_WIDTH 1		#define DMA_ISR_MACIS_WIDTH 1
#define DMA_ISR_MTLIS_INDEX 16		#define DMA_ISR_MTLIS_INDEX 16
#define DMA_ISR_MTLIS_WIDTH 1		#define DMA_ISR_MTLIS_WIDTH 1
		#define DMA_MR_INTM_INDEX 12
		#define DMA_MR_INTM_WIDTH 2
#define DMA_MR_SWR_INDEX 0		#define DMA_MR_SWR_INDEX 0
#define DMA_MR_SWR_WIDTH 1		#define DMA_MR_SWR_WIDTH 1
		#define DMA_RXEDMACR_RDPS_INDEX 0
		#define DMA_RXEDMACR_RDPS_WIDTH 3
		#define DMA_SBMR_AAL_INDEX 12
		#define DMA_SBMR_AAL_WIDTH 1
#define DMA_SBMR_EAME_INDEX 11		#define DMA_SBMR_EAME_INDEX 11
#define DMA_SBMR_EAME_WIDTH 1		#define DMA_SBMR_EAME_WIDTH 1
#define DMA_SBMR_BLEN_256_INDEX 7		#define DMA_SBMR_BLEN_INDEX 1
#define DMA_SBMR_BLEN_256_WIDTH 1		#define DMA_SBMR_BLEN_WIDTH 7
		#define DMA_SBMR_RD_OSR_LMT_INDEX 16
		#define DMA_SBMR_RD_OSR_LMT_WIDTH 6
#define DMA_SBMR_UNDEF_INDEX 0		#define DMA_SBMR_UNDEF_INDEX 0
#define DMA_SBMR_UNDEF_WIDTH 1		#define DMA_SBMR_UNDEF_WIDTH 1
		#define DMA_SBMR_WR_OSR_LMT_INDEX 24
		#define DMA_SBMR_WR_OSR_LMT_WIDTH 6
		#define DMA_TXEDMACR_TDPS_INDEX 0
		#define DMA_TXEDMACR_TDPS_WIDTH 3

/* DMA register values */		/* DMA register values */
		#define DMA_SBMR_BLEN_256 256
		#define DMA_SBMR_BLEN_128 128
		#define DMA_SBMR_BLEN_64 64
		#define DMA_SBMR_BLEN_32 32
		#define DMA_SBMR_BLEN_16 16
		#define DMA_SBMR_BLEN_8 8
		#define DMA_SBMR_BLEN_4 4
#define DMA_DSR_RPS_WIDTH 4		#define DMA_DSR_RPS_WIDTH 4
#define DMA_DSR_TPS_WIDTH 4		#define DMA_DSR_TPS_WIDTH 4
#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)		#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
#define DMA_DSR0_RPS_START 8		#define DMA_DSR0_RPS_START 8
#define DMA_DSR0_TPS_START 12		#define DMA_DSR0_TPS_START 12
#define DMA_DSRX_FIRST_QUEUE 3		#define DMA_DSRX_FIRST_QUEUE 3
#define DMA_DSRX_INC 4		#define DMA_DSRX_INC 4
#define DMA_DSRX_QPR 4		#define DMA_DSRX_QPR 4
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#define DMA_CH_RIWT 0x3c		#define DMA_CH_RIWT 0x3c
#define DMA_CH_CATDR_LO 0x44		#define DMA_CH_CATDR_LO 0x44
#define DMA_CH_CARDR_LO 0x4c		#define DMA_CH_CARDR_LO 0x4c
#define DMA_CH_CATBR_HI 0x50		#define DMA_CH_CATBR_HI 0x50
#define DMA_CH_CATBR_LO 0x54		#define DMA_CH_CATBR_LO 0x54
#define DMA_CH_CARBR_HI 0x58		#define DMA_CH_CARBR_HI 0x58
#define DMA_CH_CARBR_LO 0x5c		#define DMA_CH_CARBR_LO 0x5c
#define DMA_CH_SR 0x60		#define DMA_CH_SR 0x60
		#define DMA_CH_DSR 0x64
		#define DMA_CH_DCFL 0x68
		#define DMA_CH_MFC 0x6c
		#define DMA_CH_TDTRO 0x70
		#define DMA_CH_RDTRO 0x74
		#define DMA_CH_TDWRO 0x78
		#define DMA_CH_RDWRO 0x7C

/* DMA channel register entry bit positions and sizes */		/* DMA channel register entry bit positions and sizes */
#define DMA_CH_CR_PBLX8_INDEX 16		#define DMA_CH_CR_PBLX8_INDEX 16
#define DMA_CH_CR_PBLX8_WIDTH 1		#define DMA_CH_CR_PBLX8_WIDTH 1
#define DMA_CH_CR_SPH_INDEX 24		#define DMA_CH_CR_SPH_INDEX 24
#define DMA_CH_CR_SPH_WIDTH 1		#define DMA_CH_CR_SPH_WIDTH 1
#define DMA_CH_IER_AIE_INDEX 15		#define DMA_CH_IER_AIE20_INDEX 15
		#define DMA_CH_IER_AIE20_WIDTH 1
		#define DMA_CH_IER_AIE_INDEX 14
#define DMA_CH_IER_AIE_WIDTH 1		#define DMA_CH_IER_AIE_WIDTH 1
#define DMA_CH_IER_FBEE_INDEX 12		#define DMA_CH_IER_FBEE_INDEX 12
#define DMA_CH_IER_FBEE_WIDTH 1		#define DMA_CH_IER_FBEE_WIDTH 1
#define DMA_CH_IER_NIE_INDEX 16		#define DMA_CH_IER_NIE20_INDEX 16
		#define DMA_CH_IER_NIE20_WIDTH 1
		#define DMA_CH_IER_NIE_INDEX 15
#define DMA_CH_IER_NIE_WIDTH 1		#define DMA_CH_IER_NIE_WIDTH 1
#define DMA_CH_IER_RBUE_INDEX 7		#define DMA_CH_IER_RBUE_INDEX 7
#define DMA_CH_IER_RBUE_WIDTH 1		#define DMA_CH_IER_RBUE_WIDTH 1
#define DMA_CH_IER_RIE_INDEX 6		#define DMA_CH_IER_RIE_INDEX 6
#define DMA_CH_IER_RIE_WIDTH 1		#define DMA_CH_IER_RIE_WIDTH 1
#define DMA_CH_IER_RSE_INDEX 8		#define DMA_CH_IER_RSE_INDEX 8
#define DMA_CH_IER_RSE_WIDTH 1		#define DMA_CH_IER_RSE_WIDTH 1
#define DMA_CH_IER_TBUE_INDEX 2		#define DMA_CH_IER_TBUE_INDEX 2
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#define DMA_PBL_X8_ENABLE 0x01		#define DMA_PBL_X8_ENABLE 0x01

/* MAC register offsets */		/* MAC register offsets */
#define MAC_TCR 0x0000		#define MAC_TCR 0x0000
#define MAC_RCR 0x0004		#define MAC_RCR 0x0004
#define MAC_PFR 0x0008		#define MAC_PFR 0x0008
#define MAC_WTR 0x000c		#define MAC_WTR 0x000c
#define MAC_HTR0 0x0010		#define MAC_HTR0 0x0010
		#define MAC_HTR1 0x0014
		#define MAC_HTR2 0x0018
		#define MAC_HTR3 0x001c
		#define MAC_HTR4 0x0020
		#define MAC_HTR5 0x0024
		#define MAC_HTR6 0x0028
		#define MAC_HTR7 0x002c
#define MAC_VLANTR 0x0050		#define MAC_VLANTR 0x0050
#define MAC_VLANHTR 0x0058		#define MAC_VLANHTR 0x0058
#define MAC_VLANIR 0x0060		#define MAC_VLANIR 0x0060
#define MAC_IVLANIR 0x0064		#define MAC_IVLANIR 0x0064
#define MAC_RETMR 0x006c		#define MAC_RETMR 0x006c
#define MAC_Q0TFCR 0x0070		#define MAC_Q0TFCR 0x0070
		#define MAC_Q1TFCR 0x0074
		#define MAC_Q2TFCR 0x0078
		#define MAC_Q3TFCR 0x007c
		#define MAC_Q4TFCR 0x0080
		#define MAC_Q5TFCR 0x0084
		#define MAC_Q6TFCR 0x0088
		#define MAC_Q7TFCR 0x008c
#define MAC_RFCR 0x0090		#define MAC_RFCR 0x0090
#define MAC_RQC0R 0x00a0		#define MAC_RQC0R 0x00a0
#define MAC_RQC1R 0x00a4		#define MAC_RQC1R 0x00a4
#define MAC_RQC2R 0x00a8		#define MAC_RQC2R 0x00a8
#define MAC_RQC3R 0x00ac		#define MAC_RQC3R 0x00ac
#define MAC_ISR 0x00b0		#define MAC_ISR 0x00b0
#define MAC_IER 0x00b4		#define MAC_IER 0x00b4
#define MAC_RTSR 0x00b8		#define MAC_RTSR 0x00b8
#define MAC_PMTCSR 0x00c0		#define MAC_PMTCSR 0x00c0
#define MAC_RWKPFR 0x00c4		#define MAC_RWKPFR 0x00c4
#define MAC_LPICSR 0x00d0		#define MAC_LPICSR 0x00d0
#define MAC_LPITCR 0x00d4		#define MAC_LPITCR 0x00d4
		#define MAC_TIR 0x00e0
#define MAC_VR 0x0110		#define MAC_VR 0x0110
#define MAC_DR 0x0114		#define MAC_DR 0x0114
#define MAC_HWF0R 0x011c		#define MAC_HWF0R 0x011c
#define MAC_HWF1R 0x0120		#define MAC_HWF1R 0x0120
#define MAC_HWF2R 0x0124		#define MAC_HWF2R 0x0124
		#define MAC_MDIOSCAR 0x0200
		#define MAC_MDIOSCCDR 0x0204
		#define MAC_MDIOISR 0x0214
		#define MAC_MDIOIER 0x0218
		#define MAC_MDIOCL22R 0x0220
#define MAC_GPIOCR 0x0278		#define MAC_GPIOCR 0x0278
#define MAC_GPIOSR 0x027c		#define MAC_GPIOSR 0x027c
#define MAC_MACA0HR 0x0300		#define MAC_MACA0HR 0x0300
#define MAC_MACA0LR 0x0304		#define MAC_MACA0LR 0x0304
#define MAC_MACA1HR 0x0308		#define MAC_MACA1HR 0x0308
#define MAC_MACA1LR 0x030c		#define MAC_MACA1LR 0x030c
#define MAC_RSSCR 0x0c80		#define MAC_RSSCR 0x0c80
#define MAC_RSSAR 0x0c88		#define MAC_RSSAR 0x0c88
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#define MAC_HWF0R_TSSEL_INDEX 12		#define MAC_HWF0R_TSSEL_INDEX 12
#define MAC_HWF0R_TSSEL_WIDTH 1		#define MAC_HWF0R_TSSEL_WIDTH 1
#define MAC_HWF0R_TSSTSSEL_INDEX 25		#define MAC_HWF0R_TSSTSSEL_INDEX 25
#define MAC_HWF0R_TSSTSSEL_WIDTH 2		#define MAC_HWF0R_TSSTSSEL_WIDTH 2
#define MAC_HWF0R_TXCOESEL_INDEX 14		#define MAC_HWF0R_TXCOESEL_INDEX 14
#define MAC_HWF0R_TXCOESEL_WIDTH 1		#define MAC_HWF0R_TXCOESEL_WIDTH 1
#define MAC_HWF0R_VLHASH_INDEX 4		#define MAC_HWF0R_VLHASH_INDEX 4
#define MAC_HWF0R_VLHASH_WIDTH 1		#define MAC_HWF0R_VLHASH_WIDTH 1
		#define MAC_HWF0R_VXN_INDEX 29
		#define MAC_HWF0R_VXN_WIDTH 1
#define MAC_HWF1R_ADDR64_INDEX 14		#define MAC_HWF1R_ADDR64_INDEX 14
#define MAC_HWF1R_ADDR64_WIDTH 2		#define MAC_HWF1R_ADDR64_WIDTH 2
#define MAC_HWF1R_ADVTHWORD_INDEX 13		#define MAC_HWF1R_ADVTHWORD_INDEX 13
#define MAC_HWF1R_ADVTHWORD_WIDTH 1		#define MAC_HWF1R_ADVTHWORD_WIDTH 1
#define MAC_HWF1R_DBGMEMA_INDEX 19		#define MAC_HWF1R_DBGMEMA_INDEX 19
#define MAC_HWF1R_DBGMEMA_WIDTH 1		#define MAC_HWF1R_DBGMEMA_WIDTH 1
#define MAC_HWF1R_DCBEN_INDEX 16		#define MAC_HWF1R_DCBEN_INDEX 16
#define MAC_HWF1R_DCBEN_WIDTH 1		#define MAC_HWF1R_DCBEN_WIDTH 1
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#define MAC_IER_TSIE_INDEX 12		#define MAC_IER_TSIE_INDEX 12
#define MAC_IER_TSIE_WIDTH 1		#define MAC_IER_TSIE_WIDTH 1
#define MAC_ISR_MMCRXIS_INDEX 9		#define MAC_ISR_MMCRXIS_INDEX 9
#define MAC_ISR_MMCRXIS_WIDTH 1		#define MAC_ISR_MMCRXIS_WIDTH 1
#define MAC_ISR_MMCTXIS_INDEX 10		#define MAC_ISR_MMCTXIS_INDEX 10
#define MAC_ISR_MMCTXIS_WIDTH 1		#define MAC_ISR_MMCTXIS_WIDTH 1
#define MAC_ISR_PMTIS_INDEX 4		#define MAC_ISR_PMTIS_INDEX 4
#define MAC_ISR_PMTIS_WIDTH 1		#define MAC_ISR_PMTIS_WIDTH 1
		#define MAC_ISR_SMI_INDEX 1
		#define MAC_ISR_SMI_WIDTH 1
#define MAC_ISR_TSIS_INDEX 12		#define MAC_ISR_TSIS_INDEX 12
#define MAC_ISR_TSIS_WIDTH 1		#define MAC_ISR_TSIS_WIDTH 1
#define MAC_MACA1HR_AE_INDEX 31		#define MAC_MACA1HR_AE_INDEX 31
#define MAC_MACA1HR_AE_WIDTH 1		#define MAC_MACA1HR_AE_WIDTH 1
		#define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
		#define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
		#define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
		#define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
		#define MAC_MDIOSCAR_DA_INDEX 21
		#define MAC_MDIOSCAR_DA_WIDTH 5
		#define MAC_MDIOSCAR_PA_INDEX 16
		#define MAC_MDIOSCAR_PA_WIDTH 5
		#define MAC_MDIOSCAR_RA_INDEX 0
		#define MAC_MDIOSCAR_RA_WIDTH 16
		#define MAC_MDIOSCCDR_BUSY_INDEX 22
		#define MAC_MDIOSCCDR_BUSY_WIDTH 1
		#define MAC_MDIOSCCDR_CMD_INDEX 16
		#define MAC_MDIOSCCDR_CMD_WIDTH 2
		#define MAC_MDIOSCCDR_CR_INDEX 19
		#define MAC_MDIOSCCDR_CR_WIDTH 3
		#define MAC_MDIOSCCDR_DATA_INDEX 0
		#define MAC_MDIOSCCDR_DATA_WIDTH 16
		#define MAC_MDIOSCCDR_SADDR_INDEX 18
		#define MAC_MDIOSCCDR_SADDR_WIDTH 1
#define MAC_PFR_HMC_INDEX 2		#define MAC_PFR_HMC_INDEX 2
#define MAC_PFR_HMC_WIDTH 1		#define MAC_PFR_HMC_WIDTH 1
#define MAC_PFR_HPF_INDEX 10		#define MAC_PFR_HPF_INDEX 10
#define MAC_PFR_HPF_WIDTH 1		#define MAC_PFR_HPF_WIDTH 1
#define MAC_PFR_HUC_INDEX 1		#define MAC_PFR_HUC_INDEX 1
#define MAC_PFR_HUC_WIDTH 1		#define MAC_PFR_HUC_WIDTH 1
#define MAC_PFR_PM_INDEX 4		#define MAC_PFR_PM_INDEX 4
#define MAC_PFR_PM_WIDTH 1		#define MAC_PFR_PM_WIDTH 1
#define MAC_PFR_PR_INDEX 0		#define MAC_PFR_PR_INDEX 0
#define MAC_PFR_PR_WIDTH 1		#define MAC_PFR_PR_WIDTH 1
#define MAC_PFR_VTFE_INDEX 16		#define MAC_PFR_VTFE_INDEX 16
#define MAC_PFR_VTFE_WIDTH 1		#define MAC_PFR_VTFE_WIDTH 1
		#define MAC_PFR_VUCC_INDEX 22
		#define MAC_PFR_VUCC_WIDTH 1
#define MAC_PMTCSR_MGKPKTEN_INDEX 1		#define MAC_PMTCSR_MGKPKTEN_INDEX 1
#define MAC_PMTCSR_MGKPKTEN_WIDTH 1		#define MAC_PMTCSR_MGKPKTEN_WIDTH 1
#define MAC_PMTCSR_PWRDWN_INDEX 0		#define MAC_PMTCSR_PWRDWN_INDEX 0
#define MAC_PMTCSR_PWRDWN_WIDTH 1		#define MAC_PMTCSR_PWRDWN_WIDTH 1
#define MAC_PMTCSR_RWKFILTRST_INDEX 31		#define MAC_PMTCSR_RWKFILTRST_INDEX 31
#define MAC_PMTCSR_RWKFILTRST_WIDTH 1		#define MAC_PMTCSR_RWKFILTRST_WIDTH 1
#define MAC_PMTCSR_RWKPKTEN_INDEX 2		#define MAC_PMTCSR_RWKPKTEN_INDEX 2
#define MAC_PMTCSR_RWKPKTEN_WIDTH 1		#define MAC_PMTCSR_RWKPKTEN_WIDTH 1
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#define MAC_RCR_IPC_INDEX 9		#define MAC_RCR_IPC_INDEX 9
#define MAC_RCR_IPC_WIDTH 1		#define MAC_RCR_IPC_WIDTH 1
#define MAC_RCR_JE_INDEX 8		#define MAC_RCR_JE_INDEX 8
#define MAC_RCR_JE_WIDTH 1		#define MAC_RCR_JE_WIDTH 1
#define MAC_RCR_LM_INDEX 10		#define MAC_RCR_LM_INDEX 10
#define MAC_RCR_LM_WIDTH 1		#define MAC_RCR_LM_WIDTH 1
#define MAC_RCR_RE_INDEX 0		#define MAC_RCR_RE_INDEX 0
#define MAC_RCR_RE_WIDTH 1		#define MAC_RCR_RE_WIDTH 1
		#define MAC_RCR_ARPEN_INDEX 31
		#define MAC_RCR_ARPEN_WIDTH 1
#define MAC_RFCR_PFCE_INDEX 8		#define MAC_RFCR_PFCE_INDEX 8
#define MAC_RFCR_PFCE_WIDTH 1		#define MAC_RFCR_PFCE_WIDTH 1
#define MAC_RFCR_RFE_INDEX 0		#define MAC_RFCR_RFE_INDEX 0
#define MAC_RFCR_RFE_WIDTH 1		#define MAC_RFCR_RFE_WIDTH 1
#define MAC_RFCR_UP_INDEX 1		#define MAC_RFCR_UP_INDEX 1
#define MAC_RFCR_UP_WIDTH 1		#define MAC_RFCR_UP_WIDTH 1
#define MAC_RQC0R_RXQ0EN_INDEX 0		#define MAC_RQC0R_RXQ0EN_INDEX 0
#define MAC_RQC0R_RXQ0EN_WIDTH 2		#define MAC_RQC0R_RXQ0EN_WIDTH 2
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#define MAC_SSIR_SNSINC_INDEX 8		#define MAC_SSIR_SNSINC_INDEX 8
#define MAC_SSIR_SNSINC_WIDTH 8		#define MAC_SSIR_SNSINC_WIDTH 8
#define MAC_SSIR_SSINC_INDEX 16		#define MAC_SSIR_SSINC_INDEX 16
#define MAC_SSIR_SSINC_WIDTH 8		#define MAC_SSIR_SSINC_WIDTH 8
#define MAC_TCR_SS_INDEX 29		#define MAC_TCR_SS_INDEX 29
#define MAC_TCR_SS_WIDTH 2		#define MAC_TCR_SS_WIDTH 2
#define MAC_TCR_TE_INDEX 0		#define MAC_TCR_TE_INDEX 0
#define MAC_TCR_TE_WIDTH 1		#define MAC_TCR_TE_WIDTH 1
		#define MAC_TCR_VNE_INDEX 24
		#define MAC_TCR_VNE_WIDTH 1
		#define MAC_TCR_VNM_INDEX 25
		#define MAC_TCR_VNM_WIDTH 1
		#define MAC_TIR_TNID_INDEX 0
		#define MAC_TIR_TNID_WIDTH 16
#define MAC_TSCR_AV8021ASMEN_INDEX 28		#define MAC_TSCR_AV8021ASMEN_INDEX 28
#define MAC_TSCR_AV8021ASMEN_WIDTH 1		#define MAC_TSCR_AV8021ASMEN_WIDTH 1
#define MAC_TSCR_SNAPTYPSEL_INDEX 16		#define MAC_TSCR_SNAPTYPSEL_INDEX 16
#define MAC_TSCR_SNAPTYPSEL_WIDTH 2		#define MAC_TSCR_SNAPTYPSEL_WIDTH 2
#define MAC_TSCR_TSADDREG_INDEX 5		#define MAC_TSCR_TSADDREG_INDEX 5
#define MAC_TSCR_TSADDREG_WIDTH 1		#define MAC_TSCR_TSADDREG_WIDTH 1
#define MAC_TSCR_TSCFUPDT_INDEX 1		#define MAC_TSCR_TSCFUPDT_INDEX 1
#define MAC_TSCR_TSCFUPDT_WIDTH 1		#define MAC_TSCR_TSCFUPDT_WIDTH 1
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/* MTL register offsets */		/* MTL register offsets */
#define MTL_OMR 0x1000		#define MTL_OMR 0x1000
#define MTL_FDCR 0x1008		#define MTL_FDCR 0x1008
#define MTL_FDSR 0x100c		#define MTL_FDSR 0x100c
#define MTL_FDDR 0x1010		#define MTL_FDDR 0x1010
#define MTL_ISR 0x1020		#define MTL_ISR 0x1020
#define MTL_RQDCM0R 0x1030		#define MTL_RQDCM0R 0x1030
		#define MTL_RQDCM1R 0x1034
		#define MTL_RQDCM2R 0x1038
#define MTL_TCPM0R 0x1040		#define MTL_TCPM0R 0x1040
#define MTL_TCPM1R 0x1044		#define MTL_TCPM1R 0x1044

#define MTL_RQDCM_INC 4		#define MTL_RQDCM_INC 4
#define MTL_RQDCM_Q_PER_REG 4		#define MTL_RQDCM_Q_PER_REG 4
#define MTL_TCPM_INC 4		#define MTL_TCPM_INC 4
#define MTL_TCPM_TC_PER_REG 4		#define MTL_TCPM_TC_PER_REG 4

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* are accessed using an offset of 0x80 from the previous queue.		* are accessed using an offset of 0x80 from the previous queue.
*/		*/
#define MTL_Q_BASE 0x1100		#define MTL_Q_BASE 0x1100
#define MTL_Q_INC 0x80		#define MTL_Q_INC 0x80

#define MTL_Q_TQOMR 0x00		#define MTL_Q_TQOMR 0x00
#define MTL_Q_TQUR 0x04		#define MTL_Q_TQUR 0x04
#define MTL_Q_TQDR 0x08		#define MTL_Q_TQDR 0x08
		#define MTL_Q_TC0ETSCR 0x10
		#define MTL_Q_TC0ETSSR 0x14
		#define MTL_Q_TC0QWR 0x18
#define MTL_Q_RQOMR 0x40		#define MTL_Q_RQOMR 0x40
#define MTL_Q_RQMPOCR 0x44		#define MTL_Q_RQMPOCR 0x44
#define MTL_Q_RQDR 0x48		#define MTL_Q_RQDR 0x48
		#define MTL_Q_RQCR 0x4c
#define MTL_Q_RQFCR 0x50		#define MTL_Q_RQFCR 0x50
#define MTL_Q_IER 0x70		#define MTL_Q_IER 0x70
#define MTL_Q_ISR 0x74		#define MTL_Q_ISR 0x74

/* MTL queue register entry bit positions and sizes */		/* MTL queue register entry bit positions and sizes */
#define MTL_Q_RQDR_PRXQ_INDEX 16		#define MTL_Q_RQDR_PRXQ_INDEX 16
#define MTL_Q_RQDR_PRXQ_WIDTH 14		#define MTL_Q_RQDR_PRXQ_WIDTH 14
#define MTL_Q_RQDR_RXQSTS_INDEX 4		#define MTL_Q_RQDR_RXQSTS_INDEX 4
#define MTL_Q_RQDR_RXQSTS_WIDTH 2		#define MTL_Q_RQDR_RXQSTS_WIDTH 2
#define MTL_Q_RQFCR_RFA_INDEX 1		#define MTL_Q_RQFCR_RFA_INDEX 1
#define MTL_Q_RQFCR_RFA_WIDTH 6		#define MTL_Q_RQFCR_RFA_WIDTH 6
#define MTL_Q_RQFCR_RFD_INDEX 17		#define MTL_Q_RQFCR_RFD_INDEX 17
#define MTL_Q_RQFCR_RFD_WIDTH 6		#define MTL_Q_RQFCR_RFD_WIDTH 6
#define MTL_Q_RQOMR_EHFC_INDEX 7		#define MTL_Q_RQOMR_EHFC_INDEX 7
#define MTL_Q_RQOMR_EHFC_WIDTH 1		#define MTL_Q_RQOMR_EHFC_WIDTH 1
#define MTL_Q_RQOMR_RQS_INDEX 16		#define MTL_Q_RQOMR_RQS_INDEX 16
#define MTL_Q_RQOMR_RQS_WIDTH 9		#define MTL_Q_RQOMR_RQS_WIDTH 9
#define MTL_Q_RQOMR_RSF_INDEX 5		#define MTL_Q_RQOMR_RSF_INDEX 5
#define MTL_Q_RQOMR_RSF_WIDTH 1		#define MTL_Q_RQOMR_RSF_WIDTH 1
#define MTL_Q_RQOMR_RTC_INDEX 0		#define MTL_Q_RQOMR_RTC_INDEX 0
#define MTL_Q_RQOMR_RTC_WIDTH 2		#define MTL_Q_RQOMR_RTC_WIDTH 2
		#define MTL_Q_TQDR_TRCSTS_INDEX 1
		#define MTL_Q_TQDR_TRCSTS_WIDTH 2
		#define MTL_Q_TQDR_TXQSTS_INDEX 4
		#define MTL_Q_TQDR_TXQSTS_WIDTH 1
#define MTL_Q_TQOMR_FTQ_INDEX 0		#define MTL_Q_TQOMR_FTQ_INDEX 0
#define MTL_Q_TQOMR_FTQ_WIDTH 1		#define MTL_Q_TQOMR_FTQ_WIDTH 1
#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8		#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3		#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
#define MTL_Q_TQOMR_TQS_INDEX 16		#define MTL_Q_TQOMR_TQS_INDEX 16
#define MTL_Q_TQOMR_TQS_WIDTH 10		#define MTL_Q_TQOMR_TQS_WIDTH 10
#define MTL_Q_TQOMR_TSF_INDEX 1		#define MTL_Q_TQOMR_TSF_INDEX 1
#define MTL_Q_TQOMR_TSF_WIDTH 1		#define MTL_Q_TQOMR_TSF_WIDTH 1
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/* PCS MMD select register offset		/* PCS MMD select register offset
* The MMD select register is used for accessing PCS registers		* The MMD select register is used for accessing PCS registers
* when the underlying APB3 interface is using indirect addressing.		* when the underlying APB3 interface is using indirect addressing.
* Indirect addressing requires accessing registers in two phases,		* Indirect addressing requires accessing registers in two phases,
* an address phase and a data phase. The address phases requires		* an address phase and a data phase. The address phases requires
* writing an address selection value to the MMD select regiesters.		* writing an address selection value to the MMD select regiesters.
*/		*/
#define PCS_MMD_SELECT 0xff		#define PCS_V1_WINDOW_SELECT 0x03fc
		#define PCS_V2_WINDOW_DEF 0x9060
		#define PCS_V2_WINDOW_SELECT 0x9064
		#define PCS_V2_RV_WINDOW_DEF 0x1060
		#define PCS_V2_RV_WINDOW_SELECT 0x1064

		/* PCS register entry bit positions and sizes */
		#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
		#define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
		#define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
		#define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4

/* SerDes integration register offsets */		/* SerDes integration register offsets */
#define SIR0_KR_RT_1 0x002c		#define SIR0_KR_RT_1 0x002c
#define SIR0_STATUS 0x0040		#define SIR0_STATUS 0x0040
#define SIR1_SPEED 0x0000		#define SIR1_SPEED 0x0000

/* SerDes integration register entry bit positions and sizes */		/* SerDes integration register entry bit positions and sizes */
#define SIR0_KR_RT_1_RESET_INDEX 11		#define SIR0_KR_RT_1_RESET_INDEX 11
#define SIR0_KR_RT_1_RESET_WIDTH 1		#define SIR0_KR_RT_1_RESET_WIDTH 1
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#define RXTX_REG6_RESETB_RXD_WIDTH 1		#define RXTX_REG6_RESETB_RXD_WIDTH 1
#define RXTX_REG20_BLWC_ENA_INDEX 2		#define RXTX_REG20_BLWC_ENA_INDEX 2
#define RXTX_REG20_BLWC_ENA_WIDTH 1		#define RXTX_REG20_BLWC_ENA_WIDTH 1
#define RXTX_REG114_PQ_REG_INDEX 9		#define RXTX_REG114_PQ_REG_INDEX 9
#define RXTX_REG114_PQ_REG_WIDTH 7		#define RXTX_REG114_PQ_REG_WIDTH 7
#define RXTX_REG129_RXDFE_CONFIG_INDEX 14		#define RXTX_REG129_RXDFE_CONFIG_INDEX 14
#define RXTX_REG129_RXDFE_CONFIG_WIDTH 2		#define RXTX_REG129_RXDFE_CONFIG_WIDTH 2

		/* MAC Control register offsets */
		#define XP_PROP_0 0x0000
		#define XP_PROP_1 0x0004
		#define XP_PROP_2 0x0008
		#define XP_PROP_3 0x000c
		#define XP_PROP_4 0x0010
		#define XP_PROP_5 0x0014
		#define XP_MAC_ADDR_LO 0x0020
		#define XP_MAC_ADDR_HI 0x0024
		#define XP_ECC_ISR 0x0030
		#define XP_ECC_IER 0x0034
		#define XP_ECC_CNT0 0x003c
		#define XP_ECC_CNT1 0x0040
		#define XP_DRIVER_INT_REQ 0x0060
		#define XP_DRIVER_INT_RO 0x0064
		#define XP_DRIVER_SCRATCH_0 0x0068
		#define XP_DRIVER_SCRATCH_1 0x006c
		#define XP_INT_REISSUE_EN 0x0074
		#define XP_INT_EN 0x0078
		#define XP_I2C_MUTEX 0x0080
		#define XP_MDIO_MUTEX 0x0084

		/* MAC Control register entry bit positions and sizes */
		#define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
		#define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
		#define XP_DRIVER_INT_RO_STATUS_INDEX 0
		#define XP_DRIVER_INT_RO_STATUS_WIDTH 1
		#define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
		#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
		#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
		#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
		#define XP_ECC_CNT0_RX_DED_INDEX 24
		#define XP_ECC_CNT0_RX_DED_WIDTH 8
		#define XP_ECC_CNT0_RX_SEC_INDEX 16
		#define XP_ECC_CNT0_RX_SEC_WIDTH 8
		#define XP_ECC_CNT0_TX_DED_INDEX 8
		#define XP_ECC_CNT0_TX_DED_WIDTH 8
		#define XP_ECC_CNT0_TX_SEC_INDEX 0
		#define XP_ECC_CNT0_TX_SEC_WIDTH 8
		#define XP_ECC_CNT1_DESC_DED_INDEX 8
		#define XP_ECC_CNT1_DESC_DED_WIDTH 8
		#define XP_ECC_CNT1_DESC_SEC_INDEX 0
		#define XP_ECC_CNT1_DESC_SEC_WIDTH 8
		#define XP_ECC_IER_DESC_DED_INDEX 5
		#define XP_ECC_IER_DESC_DED_WIDTH 1
		#define XP_ECC_IER_DESC_SEC_INDEX 4
		#define XP_ECC_IER_DESC_SEC_WIDTH 1
		#define XP_ECC_IER_RX_DED_INDEX 3
		#define XP_ECC_IER_RX_DED_WIDTH 1
		#define XP_ECC_IER_RX_SEC_INDEX 2
		#define XP_ECC_IER_RX_SEC_WIDTH 1
		#define XP_ECC_IER_TX_DED_INDEX 1
		#define XP_ECC_IER_TX_DED_WIDTH 1
		#define XP_ECC_IER_TX_SEC_INDEX 0
		#define XP_ECC_IER_TX_SEC_WIDTH 1
		#define XP_ECC_ISR_DESC_DED_INDEX 5
		#define XP_ECC_ISR_DESC_DED_WIDTH 1
		#define XP_ECC_ISR_DESC_SEC_INDEX 4
		#define XP_ECC_ISR_DESC_SEC_WIDTH 1
		#define XP_ECC_ISR_RX_DED_INDEX 3
		#define XP_ECC_ISR_RX_DED_WIDTH 1
		#define XP_ECC_ISR_RX_SEC_INDEX 2
		#define XP_ECC_ISR_RX_SEC_WIDTH 1
		#define XP_ECC_ISR_TX_DED_INDEX 1
		#define XP_ECC_ISR_TX_DED_WIDTH 1
		#define XP_ECC_ISR_TX_SEC_INDEX 0
		#define XP_ECC_ISR_TX_SEC_WIDTH 1
		#define XP_I2C_MUTEX_BUSY_INDEX 31
		#define XP_I2C_MUTEX_BUSY_WIDTH 1
		#define XP_I2C_MUTEX_ID_INDEX 29
		#define XP_I2C_MUTEX_ID_WIDTH 2
		#define XP_I2C_MUTEX_ACTIVE_INDEX 0
		#define XP_I2C_MUTEX_ACTIVE_WIDTH 1
		#define XP_MAC_ADDR_HI_VALID_INDEX 31
		#define XP_MAC_ADDR_HI_VALID_WIDTH 1
		#define XP_PROP_0_CONN_TYPE_INDEX 28
		#define XP_PROP_0_CONN_TYPE_WIDTH 3
		#define XP_PROP_0_MDIO_ADDR_INDEX 16
		#define XP_PROP_0_MDIO_ADDR_WIDTH 5
		#define XP_PROP_0_PORT_ID_INDEX 0
		#define XP_PROP_0_PORT_ID_WIDTH 8
		#define XP_PROP_0_PORT_MODE_INDEX 8
		#define XP_PROP_0_PORT_MODE_WIDTH 4
		#define XP_PROP_0_PORT_SPEEDS_INDEX 23
		#define XP_PROP_0_PORT_SPEEDS_WIDTH 4
		#define XP_PROP_1_MAX_RX_DMA_INDEX 24
		#define XP_PROP_1_MAX_RX_DMA_WIDTH 5
		#define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
		#define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
		#define XP_PROP_1_MAX_TX_DMA_INDEX 16
		#define XP_PROP_1_MAX_TX_DMA_WIDTH 5
		#define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
		#define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
		#define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
		#define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
		#define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
		#define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
		#define XP_PROP_3_GPIO_MASK_INDEX 28
		#define XP_PROP_3_GPIO_MASK_WIDTH 4
		#define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
		#define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
		#define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
		#define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
		#define XP_PROP_3_GPIO_RX_LOS_INDEX 24
		#define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
		#define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
		#define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
		#define XP_PROP_3_GPIO_ADDR_INDEX 8
		#define XP_PROP_3_GPIO_ADDR_WIDTH 3
		#define XP_PROP_3_MDIO_RESET_INDEX 0
		#define XP_PROP_3_MDIO_RESET_WIDTH 2
		#define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
		#define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
		#define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
		#define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
		#define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
		#define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
		#define XP_PROP_4_MUX_ADDR_HI_INDEX 8
		#define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
		#define XP_PROP_4_MUX_ADDR_LO_INDEX 0
		#define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
		#define XP_PROP_4_MUX_CHAN_INDEX 4
		#define XP_PROP_4_MUX_CHAN_WIDTH 3
		#define XP_PROP_4_REDRV_ADDR_INDEX 16
		#define XP_PROP_4_REDRV_ADDR_WIDTH 7
		#define XP_PROP_4_REDRV_IF_INDEX 23
		#define XP_PROP_4_REDRV_IF_WIDTH 1
		#define XP_PROP_4_REDRV_LANE_INDEX 24
		#define XP_PROP_4_REDRV_LANE_WIDTH 3
		#define XP_PROP_4_REDRV_MODEL_INDEX 28
		#define XP_PROP_4_REDRV_MODEL_WIDTH 3
		#define XP_PROP_4_REDRV_PRESENT_INDEX 31
		#define XP_PROP_4_REDRV_PRESENT_WIDTH 1

		/* I2C Control register offsets */
		#define IC_CON 0x0000
		#define IC_TAR 0x0004
		#define IC_DATA_CMD 0x0010
		#define IC_INTR_STAT 0x002c
		#define IC_INTR_MASK 0x0030
		#define IC_RAW_INTR_STAT 0x0034
		#define IC_CLR_INTR 0x0040
		#define IC_CLR_TX_ABRT 0x0054
		#define IC_CLR_STOP_DET 0x0060
		#define IC_ENABLE 0x006c
		#define IC_TXFLR 0x0074
		#define IC_RXFLR 0x0078
		#define IC_TX_ABRT_SOURCE 0x0080
		#define IC_ENABLE_STATUS 0x009c
		#define IC_COMP_PARAM_1 0x00f4

		/* I2C Control register entry bit positions and sizes */
		#define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
		#define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
		#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
		#define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
		#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
		#define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
		#define IC_CON_MASTER_MODE_INDEX 0
		#define IC_CON_MASTER_MODE_WIDTH 1
		#define IC_CON_RESTART_EN_INDEX 5
		#define IC_CON_RESTART_EN_WIDTH 1
		#define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
		#define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
		#define IC_CON_SLAVE_DISABLE_INDEX 6
		#define IC_CON_SLAVE_DISABLE_WIDTH 1
		#define IC_CON_SPEED_INDEX 1
		#define IC_CON_SPEED_WIDTH 2
		#define IC_DATA_CMD_CMD_INDEX 8
		#define IC_DATA_CMD_CMD_WIDTH 1
		#define IC_DATA_CMD_STOP_INDEX 9
		#define IC_DATA_CMD_STOP_WIDTH 1
		#define IC_ENABLE_ABORT_INDEX 1
		#define IC_ENABLE_ABORT_WIDTH 1
		#define IC_ENABLE_EN_INDEX 0
		#define IC_ENABLE_EN_WIDTH 1
		#define IC_ENABLE_STATUS_EN_INDEX 0
		#define IC_ENABLE_STATUS_EN_WIDTH 1
		#define IC_INTR_MASK_TX_EMPTY_INDEX 4
		#define IC_INTR_MASK_TX_EMPTY_WIDTH 1
		#define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
		#define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
		#define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
		#define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
		#define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
		#define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
		#define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
		#define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1

		/* I2C Control register value */
		#define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
		#define IC_TX_ABRT_ARB_LOST 0x1000

/* Descriptor/Packet entry bit positions and sizes */		/* Descriptor/Packet entry bit positions and sizes */
#define RX_PACKET_ERRORS_CRC_INDEX 2		#define RX_PACKET_ERRORS_CRC_INDEX 2
#define RX_PACKET_ERRORS_CRC_WIDTH 1		#define RX_PACKET_ERRORS_CRC_WIDTH 1
#define RX_PACKET_ERRORS_FRAME_INDEX 3		#define RX_PACKET_ERRORS_FRAME_INDEX 3
#define RX_PACKET_ERRORS_FRAME_WIDTH 1		#define RX_PACKET_ERRORS_FRAME_WIDTH 1
#define RX_PACKET_ERRORS_LENGTH_INDEX 0		#define RX_PACKET_ERRORS_LENGTH_INDEX 0
#define RX_PACKET_ERRORS_LENGTH_WIDTH 1		#define RX_PACKET_ERRORS_LENGTH_WIDTH 1
#define RX_PACKET_ERRORS_OVERRUN_INDEX 1		#define RX_PACKET_ERRORS_OVERRUN_INDEX 1
#define RX_PACKET_ERRORS_OVERRUN_WIDTH 1		#define RX_PACKET_ERRORS_OVERRUN_WIDTH 1

#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0		#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1		#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1		#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1		#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2		#define RX_PACKET_ATTRIBUTES_LAST_INDEX 2
#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1		#define RX_PACKET_ATTRIBUTES_LAST_WIDTH 1
#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3		#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1		#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4		#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1		#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5		#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1		#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6		#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1		#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
		#define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7
		#define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1
		#define RX_PACKET_ATTRIBUTES_TNP_INDEX 8
		#define RX_PACKET_ATTRIBUTES_TNP_WIDTH 1
		#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 9
		#define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 1

#define RX_NORMAL_DESC0_OVT_INDEX 0		#define RX_NORMAL_DESC0_OVT_INDEX 0
#define RX_NORMAL_DESC0_OVT_WIDTH 16		#define RX_NORMAL_DESC0_OVT_WIDTH 16
#define RX_NORMAL_DESC2_HL_INDEX 0		#define RX_NORMAL_DESC2_HL_INDEX 0
#define RX_NORMAL_DESC2_HL_WIDTH 10		#define RX_NORMAL_DESC2_HL_WIDTH 10
		#define RX_NORMAL_DESC2_TNP_INDEX 11
		#define RX_NORMAL_DESC2_TNP_WIDTH 1
		#define RX_NORMAL_DESC2_RPNG_INDEX 14
		#define RX_NORMAL_DESC2_RPNG_WIDTH 1
#define RX_NORMAL_DESC3_CDA_INDEX 27		#define RX_NORMAL_DESC3_CDA_INDEX 27
#define RX_NORMAL_DESC3_CDA_WIDTH 1		#define RX_NORMAL_DESC3_CDA_WIDTH 1
#define RX_NORMAL_DESC3_CTXT_INDEX 30		#define RX_NORMAL_DESC3_CTXT_INDEX 30
#define RX_NORMAL_DESC3_CTXT_WIDTH 1		#define RX_NORMAL_DESC3_CTXT_WIDTH 1
#define RX_NORMAL_DESC3_ES_INDEX 15		#define RX_NORMAL_DESC3_ES_INDEX 15
#define RX_NORMAL_DESC3_ES_WIDTH 1		#define RX_NORMAL_DESC3_ES_WIDTH 1
#define RX_NORMAL_DESC3_ETLT_INDEX 16		#define RX_NORMAL_DESC3_ETLT_INDEX 16
#define RX_NORMAL_DESC3_ETLT_WIDTH 4		#define RX_NORMAL_DESC3_ETLT_WIDTH 4
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#define RX_NORMAL_DESC3_PL_INDEX 0		#define RX_NORMAL_DESC3_PL_INDEX 0
#define RX_NORMAL_DESC3_PL_WIDTH 14		#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26		#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1		#define RX_NORMAL_DESC3_RSV_WIDTH 1

#define RX_DESC3_L34T_IPV4_TCP 1		#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2		#define RX_DESC3_L34T_IPV4_UDP 2
#define RX_DESC3_L34T_IPV4_ICMP 3		#define RX_DESC3_L34T_IPV4_ICMP 3
		#define RX_DESC3_L34T_IPV4_UNKNOWN 7
#define RX_DESC3_L34T_IPV6_TCP 9		#define RX_DESC3_L34T_IPV6_TCP 9
#define RX_DESC3_L34T_IPV6_UDP 10		#define RX_DESC3_L34T_IPV6_UDP 10
#define RX_DESC3_L34T_IPV6_ICMP 11		#define RX_DESC3_L34T_IPV6_ICMP 11
		#define RX_DESC3_L34T_IPV6_UNKNOWN 15

#define RX_CONTEXT_DESC3_TSA_INDEX 4		#define RX_CONTEXT_DESC3_TSA_INDEX 4
#define RX_CONTEXT_DESC3_TSA_WIDTH 1		#define RX_CONTEXT_DESC3_TSA_WIDTH 1
#define RX_CONTEXT_DESC3_TSD_INDEX 6		#define RX_CONTEXT_DESC3_TSD_INDEX 6
#define RX_CONTEXT_DESC3_TSD_WIDTH 1		#define RX_CONTEXT_DESC3_TSD_WIDTH 1

#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0		#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1		#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1		#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1		#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2		#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1		#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3		#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1		#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
		#define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 4
		#define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 1

#define TX_CONTEXT_DESC2_MSS_INDEX 0		#define TX_CONTEXT_DESC2_MSS_INDEX 0
#define TX_CONTEXT_DESC2_MSS_WIDTH 15		#define TX_CONTEXT_DESC2_MSS_WIDTH 15
#define TX_CONTEXT_DESC3_CTXT_INDEX 30		#define TX_CONTEXT_DESC3_CTXT_INDEX 30
#define TX_CONTEXT_DESC3_CTXT_WIDTH 1		#define TX_CONTEXT_DESC3_CTXT_WIDTH 1
#define TX_CONTEXT_DESC3_TCMSSV_INDEX 26		#define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1		#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
#define TX_CONTEXT_DESC3_VLTV_INDEX 16		#define TX_CONTEXT_DESC3_VLTV_INDEX 16
Show All 24 Lines
#define TX_NORMAL_DESC3_OWN_INDEX 31		#define TX_NORMAL_DESC3_OWN_INDEX 31
#define TX_NORMAL_DESC3_OWN_WIDTH 1		#define TX_NORMAL_DESC3_OWN_WIDTH 1
#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19		#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4		#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
#define TX_NORMAL_DESC3_TCPPL_INDEX 0		#define TX_NORMAL_DESC3_TCPPL_INDEX 0
#define TX_NORMAL_DESC3_TCPPL_WIDTH 18		#define TX_NORMAL_DESC3_TCPPL_WIDTH 18
#define TX_NORMAL_DESC3_TSE_INDEX 18		#define TX_NORMAL_DESC3_TSE_INDEX 18
#define TX_NORMAL_DESC3_TSE_WIDTH 1		#define TX_NORMAL_DESC3_TSE_WIDTH 1
		#define TX_NORMAL_DESC3_VNP_INDEX 23
		#define TX_NORMAL_DESC3_VNP_WIDTH 3

#define TX_NORMAL_DESC2_VLAN_INSERT 0x2		#define TX_NORMAL_DESC2_VLAN_INSERT 0x2
		#define TX_NORMAL_DESC3_VXLAN_PACKET 0x3

/* MDIO undefined or vendor specific registers */		/* MDIO undefined or vendor specific registers */
#ifndef MDIO_PMA_10GBR_PMD_CTRL		#ifndef MDIO_PMA_10GBR_PMD_CTRL
#define MDIO_PMA_10GBR_PMD_CTRL 0x0096		#define MDIO_PMA_10GBR_PMD_CTRL 0x0096
#endif		#endif

#ifndef MDIO_PMA_10GBR_FECCTRL		#ifndef MDIO_PMA_10GBR_FECCTRL
#define MDIO_PMA_10GBR_FECCTRL 0x00ab		#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif		#endif

		#ifndef MDIO_PCS_DIG_CTRL
		#define MDIO_PCS_DIG_CTRL 0x8000
		#endif

#ifndef MDIO_AN_XNP		#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP 0x0016		#define MDIO_AN_XNP 0x0016
#endif		#endif

#ifndef MDIO_AN_LPX		#ifndef MDIO_AN_LPX
#define MDIO_AN_LPX 0x0019		#define MDIO_AN_LPX 0x0019
#endif		#endif

#ifndef MDIO_AN_COMP_STAT		#ifndef MDIO_AN_COMP_STAT
#define MDIO_AN_COMP_STAT 0x0030		#define MDIO_AN_COMP_STAT 0x0030
#endif		#endif

#ifndef MDIO_AN_INTMASK		#ifndef MDIO_AN_INTMASK
#define MDIO_AN_INTMASK 0x8001		#define MDIO_AN_INTMASK 0x8001
#endif		#endif

#ifndef MDIO_AN_INT		#ifndef MDIO_AN_INT
#define MDIO_AN_INT 0x8002		#define MDIO_AN_INT 0x8002
#endif		#endif

		#ifndef MDIO_VEND2_AN_ADVERTISE
		#define MDIO_VEND2_AN_ADVERTISE 0x0004
		#endif

		#ifndef MDIO_VEND2_AN_LP_ABILITY
		#define MDIO_VEND2_AN_LP_ABILITY 0x0005
		#endif

		#ifndef MDIO_VEND2_AN_CTRL
		#define MDIO_VEND2_AN_CTRL 0x8001
		#endif

		#ifndef MDIO_VEND2_AN_STAT
		#define MDIO_VEND2_AN_STAT 0x8002
		#endif

		#ifndef MDIO_VEND2_PMA_CDR_CONTROL
		#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
		#endif

#ifndef MDIO_CTRL1_SPEED1G		#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)		#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif		#endif

		#ifndef MDIO_VEND2_CTRL1_AN_ENABLE
		#define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
		#endif

		#ifndef MDIO_VEND2_CTRL1_AN_RESTART
		#define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
		#endif

		#ifndef MDIO_VEND2_CTRL1_SS6
		#define MDIO_VEND2_CTRL1_SS6 BIT(6)
		#endif

		#ifndef MDIO_VEND2_CTRL1_SS13
		#define MDIO_VEND2_CTRL1_SS13 BIT(13)
		#endif

/* MDIO mask values */		/* MDIO mask values */
		#define XGBE_AN_CL73_INT_CMPLT BIT(0)
		#define XGBE_AN_CL73_INC_LINK BIT(1)
		#define XGBE_AN_CL73_PG_RCV BIT(2)
		#define XGBE_AN_CL73_INT_MASK 0x07

#define XGBE_XNP_MCF_NULL_MESSAGE 0x001		#define XGBE_XNP_MCF_NULL_MESSAGE 0x001
#define XGBE_XNP_ACK_PROCESSED BIT(12)		#define XGBE_XNP_ACK_PROCESSED BIT(12)
#define XGBE_XNP_MP_FORMATTED BIT(13)		#define XGBE_XNP_MP_FORMATTED BIT(13)
#define XGBE_XNP_NP_EXCHANGE BIT(15)		#define XGBE_XNP_NP_EXCHANGE BIT(15)

#define XGBE_KR_TRAINING_START BIT(0)		#define XGBE_KR_TRAINING_START BIT(0)
#define XGBE_KR_TRAINING_ENABLE BIT(1)		#define XGBE_KR_TRAINING_ENABLE BIT(1)

		#define XGBE_PCS_CL37_BP BIT(12)

		#define XGBE_AN_CL37_INT_CMPLT BIT(0)
		#define XGBE_AN_CL37_INT_MASK 0x01

		#define XGBE_AN_CL37_HD_MASK 0x40
		#define XGBE_AN_CL37_FD_MASK 0x20

		#define XGBE_AN_CL37_PCS_MODE_MASK 0x06
		#define XGBE_AN_CL37_PCS_MODE_BASEX 0x00
		#define XGBE_AN_CL37_PCS_MODE_SGMII 0x04
		#define XGBE_AN_CL37_TX_CONFIG_MASK 0x08
		#define XGBE_AN_CL37_MII_CTRL_8BIT 0x0100

		#define XGBE_PMA_CDR_TRACK_EN_MASK 0x01
		#define XGBE_PMA_CDR_TRACK_EN_OFF 0x00
		#define XGBE_PMA_CDR_TRACK_EN_ON 0x01

/* Bit setting and getting macros		/* Bit setting and getting macros
* The get macro will extract the current bit field value from within		* The get macro will extract the current bit field value from within
* the variable		* the variable
*		*
* The set macro will clear the current bit field value within the		* The set macro will clear the current bit field value within the
* variable and then set the bit field of the variable to the		* variable and then set the bit field of the variable to the
* specified value		* specified value
*/		*/
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines	GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH)		_reg##_##_field##_WIDTH)

#define XGMAC_IOWRITE(_pdata, _reg, _val) \		#define XGMAC_IOWRITE(_pdata, _reg, _val) \
bus_write_4((_pdata)->xgmac_res, _reg, (_val))		bus_write_4((_pdata)->xgmac_res, _reg, (_val))

#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \		#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \		do { \
u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \		uint32_t reg_val = XGMAC_IOREAD((_pdata), _reg); \
SET_BITS(reg_val, \		SET_BITS(reg_val, \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH, (_val)); \		_reg##_##_field##_WIDTH, (_val)); \
XGMAC_IOWRITE((_pdata), _reg, reg_val); \		XGMAC_IOWRITE((_pdata), _reg, reg_val); \
} while (0)		} while (0)

/* Macros for reading or writing MTL queue or traffic class registers		/* Macros for reading or writing MTL queue or traffic class registers
* Similar to the standard read and write macros except that the		* Similar to the standard read and write macros except that the
Show All 9 Lines	GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \
_reg##_##_field##_WIDTH)		_reg##_##_field##_WIDTH)

#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \		#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
bus_write_4((_pdata)->xgmac_res, \		bus_write_4((_pdata)->xgmac_res, \
MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg, (_val))		MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg, (_val))

#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \		#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
do { \		do { \
u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \		uint32_t reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
SET_BITS(reg_val, \		SET_BITS(reg_val, \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH, (_val)); \		_reg##_##_field##_WIDTH, (_val)); \
XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \		XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
} while (0)		} while (0)

/* Macros for reading or writing DMA channel registers		/* Macros for reading or writing DMA channel registers
* Similar to the standard read and write macros except that the		* Similar to the standard read and write macros except that the
* base register value is obtained from the ring		* base register value is obtained from the ring
*/		*/
#define XGMAC_DMA_IOREAD(_channel, _reg) \		#define XGMAC_DMA_IOREAD(_channel, _reg) \
bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg)		bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg)

#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \		#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \		GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH)		_reg##_##_field##_WIDTH)

#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \		#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \
bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle, \		bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle, \
_reg, (_val))		_reg, (_val))

#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \		#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
do { \		do { \
u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \		uint32_t reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
SET_BITS(reg_val, \		SET_BITS(reg_val, \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH, (_val)); \		_reg##_##_field##_WIDTH, (_val)); \
XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \		XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
} while (0)		} while (0)

/* Macros for building, reading or writing register values or bits		/* Macros for building, reading or writing register values or bits
* within the register values of XPCS registers.		* within the register values of XPCS registers.
*/		*/
#define XPCS_IOWRITE(_pdata, _off, _val) \		#define XPCS_GET_BITS(_var, _prefix, _field) \
		GET_BITS((_var), \
		_prefix##_##_field##_INDEX, \
		_prefix##_##_field##_WIDTH)

		#define XPCS_SET_BITS(_var, _prefix, _field, _val) \
		SET_BITS((_var), \
		_prefix##_##_field##_INDEX, \
		_prefix##_##_field##_WIDTH, (_val))

		#define XPCS32_IOWRITE(_pdata, _off, _val) \
bus_write_4((_pdata)->xpcs_res, (_off), _val)		bus_write_4((_pdata)->xpcs_res, (_off), _val)

#define XPCS_IOREAD(_pdata, _off) \		#define XPCS32_IOREAD(_pdata, _off) \
bus_read_4((_pdata)->xpcs_res, (_off))		bus_read_4((_pdata)->xpcs_res, (_off))

		#define XPCS16_IOWRITE(_pdata, _off, _val) \
		bus_write_2((_pdata)->xpcs_res, (_off), _val)

		#define XPCS16_IOREAD(_pdata, _off) \
		bus_read_2((_pdata)->xpcs_res, (_off))

/* Macros for building, reading or writing register values or bits		/* Macros for building, reading or writing register values or bits
* within the register values of SerDes integration registers.		* within the register values of SerDes integration registers.
*/		*/
#define XSIR_GET_BITS(_var, _prefix, _field) \		#define XSIR_GET_BITS(_var, _prefix, _field) \
GET_BITS((_var), \		GET_BITS((_var), \
_prefix##_##_field##_INDEX, \		_prefix##_##_field##_INDEX, \
_prefix##_##_field##_WIDTH)		_prefix##_##_field##_WIDTH)

Show All 10 Lines	GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH)		_reg##_##_field##_WIDTH)

#define XSIR0_IOWRITE(_pdata, _reg, _val) \		#define XSIR0_IOWRITE(_pdata, _reg, _val) \
bus_write_2((_pdata)->sir0_res, _reg, (_val))		bus_write_2((_pdata)->sir0_res, _reg, (_val))

#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \		#define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \		do { \
u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \		uint16_t reg_val = XSIR0_IOREAD((_pdata), _reg); \
SET_BITS(reg_val, \		SET_BITS(reg_val, \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH, (_val)); \		_reg##_##_field##_WIDTH, (_val)); \
XSIR0_IOWRITE((_pdata), _reg, reg_val); \		XSIR0_IOWRITE((_pdata), _reg, reg_val); \
} while (0)		} while (0)

#define XSIR1_IOREAD(_pdata, _reg) \		#define XSIR1_IOREAD(_pdata, _reg) \
bus_read_2((_pdata)->sir1_res, _reg)		bus_read_2((_pdata)->sir1_res, _reg)

#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \		#define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XSIR1_IOREAD((_pdata), _reg), \		GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH)		_reg##_##_field##_WIDTH)

#define XSIR1_IOWRITE(_pdata, _reg, _val) \		#define XSIR1_IOWRITE(_pdata, _reg, _val) \
bus_write_2((_pdata)->sir1_res, _reg, (_val))		bus_write_2((_pdata)->sir1_res, _reg, (_val))

#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \		#define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \		do { \
u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \		uint16_t reg_val = XSIR1_IOREAD((_pdata), _reg); \
SET_BITS(reg_val, \		SET_BITS(reg_val, \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH, (_val)); \		_reg##_##_field##_WIDTH, (_val)); \
XSIR1_IOWRITE((_pdata), _reg, reg_val); \		XSIR1_IOWRITE((_pdata), _reg, reg_val); \
} while (0)		} while (0)

/* Macros for building, reading or writing register values or bits		/* Macros for building, reading or writing register values or bits
* within the register values of SerDes RxTx registers.		* within the register values of SerDes RxTx registers.
*/		*/
#define XRXTX_IOREAD(_pdata, _reg) \		#define XRXTX_IOREAD(_pdata, _reg) \
bus_read_2((_pdata)->rxtx_res, _reg)		bus_read_2((_pdata)->rxtx_res, _reg)

#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \		#define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
GET_BITS(XRXTX_IOREAD((_pdata), _reg), \		GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH)		_reg##_##_field##_WIDTH)

#define XRXTX_IOWRITE(_pdata, _reg, _val) \		#define XRXTX_IOWRITE(_pdata, _reg, _val) \
bus_write_2((_pdata)->rxtx_res, _reg, (_val))		bus_write_2((_pdata)->rxtx_res, _reg, (_val))

#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \		#define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
do { \		do { \
u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \		uint16_t reg_val = XRXTX_IOREAD((_pdata), _reg); \
SET_BITS(reg_val, \		SET_BITS(reg_val, \
_reg##_##_field##_INDEX, \		_reg##_##_field##_INDEX, \
_reg##_##_field##_WIDTH, (_val)); \		_reg##_##_field##_WIDTH, (_val)); \
XRXTX_IOWRITE((_pdata), _reg, reg_val); \		XRXTX_IOWRITE((_pdata), _reg, reg_val); \
} while (0)		} while (0)

/* Macros for building, reading or writing register values or bits		/* Macros for building, reading or writing register values or bits
		* within the register values of MAC Control registers.
		*/
		#define XP_GET_BITS(_var, _prefix, _field) \
		GET_BITS((_var), \
		_prefix##_##_field##_INDEX, \
		_prefix##_##_field##_WIDTH)

		#define XP_SET_BITS(_var, _prefix, _field, _val) \
		SET_BITS((_var), \
		_prefix##_##_field##_INDEX, \
		_prefix##_##_field##_WIDTH, (_val))

		#define XP_IOREAD(_pdata, _reg) \
		bus_read_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET)

		#define XP_IOREAD_BITS(_pdata, _reg, _field) \
		GET_BITS(XP_IOREAD((_pdata), (_reg)), \
		_reg##_##_field##_INDEX, \
		_reg##_##_field##_WIDTH)

		#define XP_IOWRITE(_pdata, _reg, _val) \
		bus_write_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET, \
		(_val))

		#define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
		do { \
		uint32_t reg_val = XP_IOREAD((_pdata), (_reg)); \
		SET_BITS(reg_val, \
		_reg##_##_field##_INDEX, \
		_reg##_##_field##_WIDTH, (_val)); \
		XP_IOWRITE((_pdata), (_reg), reg_val); \
		} while (0)

		/* Macros for building, reading or writing register values or bits
		* within the register values of I2C Control registers.
		*/
		#define XI2C_GET_BITS(_var, _prefix, _field) \
		GET_BITS((_var), \
		_prefix##_##_field##_INDEX, \
		_prefix##_##_field##_WIDTH)

		#define XI2C_SET_BITS(_var, _prefix, _field, _val) \
		SET_BITS((_var), \
		_prefix##_##_field##_INDEX, \
		_prefix##_##_field##_WIDTH, (_val))

		#define XI2C_IOREAD(_pdata, _reg) \
		bus_read_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET)

		#define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
		GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
		_reg##_##_field##_INDEX, \
		_reg##_##_field##_WIDTH)

		#define XI2C_IOWRITE(_pdata, _reg, _val) \
		bus_write_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET, \
		(_val))

		#define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
		do { \
		uint32_t reg_val = XI2C_IOREAD((_pdata), (_reg)); \
		SET_BITS(reg_val, \
		_reg##_##_field##_INDEX, \
		_reg##_##_field##_WIDTH, (_val)); \
		XI2C_IOWRITE((_pdata), (_reg), reg_val); \
		} while (0)

		/* Macros for building, reading or writing register values or bits
* using MDIO. Different from above because of the use of standardized		* using MDIO. Different from above because of the use of standardized
* Linux include values. No shifting is performed with the bit		* Linux include values. No shifting is performed with the bit
* operations, everything works on mask values.		* operations, everything works on mask values.
*/		*/
#define XMDIO_READ(_pdata, _mmd, _reg) \		#define XMDIO_READ(_pdata, _mmd, _reg) \
((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \		((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
MII_ADDR_C45 \| (_mmd << 16) \| ((_reg) & 0xffff)))		MII_ADDR_C45 \| (_mmd << 16) \| ((_reg) & 0xffff)))

#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \		#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
(XMDIO_READ((_pdata), _mmd, _reg) & _mask)		(XMDIO_READ((_pdata), _mmd, _reg) & _mask)

#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \		#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \		((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
MII_ADDR_C45 \| (_mmd << 16) \| ((_reg) & 0xffff), (_val)))		MII_ADDR_C45 \| (_mmd << 16) \| ((_reg) & 0xffff), (_val)))

#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \		#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
do { \		do { \
u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \		uint32_t mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \
mmd_val &= ~_mask; \		mmd_val &= ~_mask; \
mmd_val \|= (_val); \		mmd_val \|= (_val); \
XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \		XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \
} while (0)		} while (0)

#endif		#endif