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sys/dev/ice/ice_controlq.h
Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines | enum ice_ctl_q { | ||||
ICE_CTL_Q_UNKNOWN = 0, | ICE_CTL_Q_UNKNOWN = 0, | ||||
ICE_CTL_Q_ADMIN, | ICE_CTL_Q_ADMIN, | ||||
ICE_CTL_Q_MAILBOX, | ICE_CTL_Q_MAILBOX, | ||||
}; | }; | ||||
/* Control Queue timeout settings - max delay 250ms */ | /* Control Queue timeout settings - max delay 250ms */ | ||||
#define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */ | #define ICE_CTL_Q_SQ_CMD_TIMEOUT 2500 /* Count 2500 times */ | ||||
#define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ | #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */ | ||||
#define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */ | |||||
#define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */ | |||||
struct ice_ctl_q_ring { | struct ice_ctl_q_ring { | ||||
void *dma_head; /* Virtual address to DMA head */ | void *dma_head; /* Virtual address to DMA head */ | ||||
struct ice_dma_mem desc_buf; /* descriptor ring memory */ | struct ice_dma_mem desc_buf; /* descriptor ring memory */ | ||||
void *cmd_buf; /* command buffer memory */ | void *cmd_buf; /* command buffer memory */ | ||||
union { | union { | ||||
struct ice_dma_mem *sq_bi; | struct ice_dma_mem *sq_bi; | ||||
Show All 9 Lines | struct ice_ctl_q_ring { | ||||
/* used for queue tracking */ | /* used for queue tracking */ | ||||
u32 head; | u32 head; | ||||
u32 tail; | u32 tail; | ||||
u32 len; | u32 len; | ||||
u32 bah; | u32 bah; | ||||
u32 bal; | u32 bal; | ||||
u32 len_mask; | u32 len_mask; | ||||
u32 len_ena_mask; | u32 len_ena_mask; | ||||
u32 len_crit_mask; | |||||
u32 head_mask; | u32 head_mask; | ||||
}; | }; | ||||
/* sq transaction details */ | /* sq transaction details */ | ||||
struct ice_sq_cd { | struct ice_sq_cd { | ||||
struct ice_aq_desc *wb_desc; | struct ice_aq_desc *wb_desc; | ||||
}; | }; | ||||
Show All 27 Lines |