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head/sys/dev/ixl/i40e_adminq_cmd.h
Show First 20 Lines • Show All 1,934 Lines • ▼ Show 20 Lines | enum i40e_aq_phy_type { | ||||
I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, | I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, | ||||
I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, | I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, | ||||
I40E_PHY_TYPE_25GBASE_KR = 0x1F, | I40E_PHY_TYPE_25GBASE_KR = 0x1F, | ||||
I40E_PHY_TYPE_25GBASE_CR = 0x20, | I40E_PHY_TYPE_25GBASE_CR = 0x20, | ||||
I40E_PHY_TYPE_25GBASE_SR = 0x21, | I40E_PHY_TYPE_25GBASE_SR = 0x21, | ||||
I40E_PHY_TYPE_25GBASE_LR = 0x22, | I40E_PHY_TYPE_25GBASE_LR = 0x22, | ||||
I40E_PHY_TYPE_25GBASE_AOC = 0x23, | I40E_PHY_TYPE_25GBASE_AOC = 0x23, | ||||
I40E_PHY_TYPE_25GBASE_ACC = 0x24, | I40E_PHY_TYPE_25GBASE_ACC = 0x24, | ||||
I40E_PHY_TYPE_2_5GBASE_T = 0x30, | |||||
I40E_PHY_TYPE_5GBASE_T = 0x31, | |||||
I40E_PHY_TYPE_MAX, | I40E_PHY_TYPE_MAX, | ||||
I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, | I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, | ||||
I40E_PHY_TYPE_EMPTY = 0xFE, | I40E_PHY_TYPE_EMPTY = 0xFE, | ||||
I40E_PHY_TYPE_DEFAULT = 0xFF, | I40E_PHY_TYPE_DEFAULT = 0xFF, | ||||
}; | }; | ||||
#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ | #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ | BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ | ||||
Show All 25 Lines | #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ | BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ | BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ | BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ | BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ | BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ | BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ | BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ | BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) | BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \ | ||||
BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \ | |||||
BIT_ULL(I40E_PHY_TYPE_5GBASE_T)) | |||||
#define I40E_LINK_SPEED_2_5GB_SHIFT 0x0 | |||||
#define I40E_LINK_SPEED_100MB_SHIFT 0x1 | #define I40E_LINK_SPEED_100MB_SHIFT 0x1 | ||||
#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 | #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 | ||||
#define I40E_LINK_SPEED_10GB_SHIFT 0x3 | #define I40E_LINK_SPEED_10GB_SHIFT 0x3 | ||||
#define I40E_LINK_SPEED_40GB_SHIFT 0x4 | #define I40E_LINK_SPEED_40GB_SHIFT 0x4 | ||||
#define I40E_LINK_SPEED_20GB_SHIFT 0x5 | #define I40E_LINK_SPEED_20GB_SHIFT 0x5 | ||||
#define I40E_LINK_SPEED_25GB_SHIFT 0x6 | #define I40E_LINK_SPEED_25GB_SHIFT 0x6 | ||||
#define I40E_LINK_SPEED_5GB_SHIFT 0x7 | |||||
enum i40e_aq_link_speed { | enum i40e_aq_link_speed { | ||||
I40E_LINK_SPEED_UNKNOWN = 0, | I40E_LINK_SPEED_UNKNOWN = 0, | ||||
I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), | I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), | ||||
I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), | I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), | ||||
I40E_LINK_SPEED_2_5GB = (1 << I40E_LINK_SPEED_2_5GB_SHIFT), | |||||
I40E_LINK_SPEED_5GB = (1 << I40E_LINK_SPEED_5GB_SHIFT), | |||||
I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), | I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), | ||||
I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), | I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), | ||||
I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), | I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), | ||||
I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), | I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), | ||||
}; | }; | ||||
struct i40e_aqc_module_desc { | struct i40e_aqc_module_desc { | ||||
u8 oui[3]; | u8 oui[3]; | ||||
Show All 20 Lines | #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 | ||||
__le16 eee_capability; | __le16 eee_capability; | ||||
#define I40E_AQ_EEE_AUTO 0x0001 | #define I40E_AQ_EEE_AUTO 0x0001 | ||||
#define I40E_AQ_EEE_100BASE_TX 0x0002 | #define I40E_AQ_EEE_100BASE_TX 0x0002 | ||||
#define I40E_AQ_EEE_1000BASE_T 0x0004 | #define I40E_AQ_EEE_1000BASE_T 0x0004 | ||||
#define I40E_AQ_EEE_10GBASE_T 0x0008 | #define I40E_AQ_EEE_10GBASE_T 0x0008 | ||||
#define I40E_AQ_EEE_1000BASE_KX 0x0010 | #define I40E_AQ_EEE_1000BASE_KX 0x0010 | ||||
#define I40E_AQ_EEE_10GBASE_KX4 0x0020 | #define I40E_AQ_EEE_10GBASE_KX4 0x0020 | ||||
#define I40E_AQ_EEE_10GBASE_KR 0x0040 | #define I40E_AQ_EEE_10GBASE_KR 0x0040 | ||||
#define I40E_AQ_EEE_2_5GBASE_T 0x0100 | |||||
#define I40E_AQ_EEE_5GBASE_T 0x0200 | |||||
__le32 eeer_val; | __le32 eeer_val; | ||||
u8 d3_lpan; | u8 d3_lpan; | ||||
#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 | #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 | ||||
u8 phy_type_ext; | u8 phy_type_ext; | ||||
#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 | #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 | ||||
#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 | #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 | ||||
#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 | #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 | ||||
#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 | #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 | ||||
#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 | #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 | ||||
#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 | #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 | ||||
#define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40 | |||||
#define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80 | |||||
u8 fec_cfg_curr_mod_ext_info; | u8 fec_cfg_curr_mod_ext_info; | ||||
#define I40E_AQ_ENABLE_FEC_KR 0x01 | #define I40E_AQ_ENABLE_FEC_KR 0x01 | ||||
#define I40E_AQ_ENABLE_FEC_RS 0x02 | #define I40E_AQ_ENABLE_FEC_RS 0x02 | ||||
#define I40E_AQ_REQUEST_FEC_KR 0x04 | #define I40E_AQ_REQUEST_FEC_KR 0x04 | ||||
#define I40E_AQ_REQUEST_FEC_RS 0x08 | #define I40E_AQ_REQUEST_FEC_RS 0x08 | ||||
#define I40E_AQ_ENABLE_FEC_AUTO 0x10 | #define I40E_AQ_ENABLE_FEC_AUTO 0x10 | ||||
#define I40E_AQ_FEC | #define I40E_AQ_FEC | ||||
#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 | #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 | ||||
▲ Show 20 Lines • Show All 226 Lines • ▼ Show 20 Lines | |||||
I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); | I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); | ||||
enum i40e_aq_phy_reg_type { | enum i40e_aq_phy_reg_type { | ||||
I40E_AQC_PHY_REG_INTERNAL = 0x1, | I40E_AQC_PHY_REG_INTERNAL = 0x1, | ||||
I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, | I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, | ||||
I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 | I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 | ||||
}; | }; | ||||
#pragma pack(1) | |||||
/* Run PHY Activity (0x0626) */ | /* Run PHY Activity (0x0626) */ | ||||
struct i40e_aqc_run_phy_activity { | struct i40e_aqc_run_phy_activity { | ||||
u8 cmd_flags; | |||||
__le16 activity_id; | __le16 activity_id; | ||||
u8 flags; | #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10 | ||||
u8 reserved1; | u8 reserved; | ||||
__le32 control; | union { | ||||
struct { | |||||
__le32 dnl_opcode; | |||||
#define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a | |||||
#define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b | |||||
#define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b | |||||
__le32 data; | __le32 data; | ||||
u8 reserved2[4]; | u8 reserved2[4]; | ||||
} cmd; | |||||
struct { | |||||
__le32 cmd_status; | |||||
#define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4 | |||||
#define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF | |||||
__le32 data0; | |||||
__le32 data1; | |||||
} resp; | |||||
} params; | |||||
}; | }; | ||||
#pragma pack() | |||||
I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); | I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); | ||||
/* Set PHY Register command (0x0628) */ | /* Set PHY Register command (0x0628) */ | ||||
/* Get PHY Register command (0x0629) */ | /* Get PHY Register command (0x0629) */ | ||||
struct i40e_aqc_phy_register_access { | struct i40e_aqc_phy_register_access { | ||||
u8 phy_interface; | u8 phy_interface; | ||||
#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 | #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 | ||||
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