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sys/amd64/include/pmap.h
Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines | |||||
#undef PG_RW | #undef PG_RW | ||||
#undef PG_V | #undef PG_V | ||||
#endif | #endif | ||||
/* | /* | ||||
* Pte related macros. This is complicated by having to deal with | * Pte related macros. This is complicated by having to deal with | ||||
* the sign extension of the 48th bit. | * the sign extension of the 48th bit. | ||||
*/ | */ | ||||
#define KVADDR(l4, l3, l2, l1) ( \ | #define KV4ADDR(l4, l3, l2, l1) ( \ | ||||
((unsigned long)-1 << 47) | \ | ((unsigned long)-1 << 47) | \ | ||||
((unsigned long)(l4) << PML4SHIFT) | \ | ((unsigned long)(l4) << PML4SHIFT) | \ | ||||
((unsigned long)(l3) << PDPSHIFT) | \ | ((unsigned long)(l3) << PDPSHIFT) | \ | ||||
((unsigned long)(l2) << PDRSHIFT) | \ | ((unsigned long)(l2) << PDRSHIFT) | \ | ||||
((unsigned long)(l1) << PAGE_SHIFT)) | ((unsigned long)(l1) << PAGE_SHIFT)) | ||||
#define KV5ADDR(l5, l4, l3, l2, l1) ( \ | |||||
((unsigned long)-1 << 56) | \ | |||||
((unsigned long)(l5) << PML5SHIFT) | \ | |||||
((unsigned long)(l4) << PML4SHIFT) | \ | |||||
((unsigned long)(l3) << PDPSHIFT) | \ | |||||
((unsigned long)(l2) << PDRSHIFT) | \ | |||||
((unsigned long)(l1) << PAGE_SHIFT)) | |||||
#define UVADDR(l4, l3, l2, l1) ( \ | #define UVADDR(l5, l4, l3, l2, l1) ( \ | ||||
((unsigned long)(l5) << PML5SHIFT) | \ | |||||
((unsigned long)(l4) << PML4SHIFT) | \ | ((unsigned long)(l4) << PML4SHIFT) | \ | ||||
((unsigned long)(l3) << PDPSHIFT) | \ | ((unsigned long)(l3) << PDPSHIFT) | \ | ||||
((unsigned long)(l2) << PDRSHIFT) | \ | ((unsigned long)(l2) << PDRSHIFT) | \ | ||||
((unsigned long)(l1) << PAGE_SHIFT)) | ((unsigned long)(l1) << PAGE_SHIFT)) | ||||
/* | /* | ||||
* Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so, | * Number of kernel PML4 slots. Can be anywhere from 1 to 64 or so, | ||||
* but setting it larger than NDMPML4E makes no sense. | * but setting it larger than NDMPML4E makes no sense. | ||||
* | * | ||||
* Each slot provides .5 TB of kernel virtual space. | * Each slot provides .5 TB of kernel virtual space. | ||||
*/ | */ | ||||
#define NKPML4E 4 | #define NKPML4E 4 | ||||
#define NUPML4E (NPML4EPG/2) /* number of userland PML4 pages */ | /* | ||||
#define NUPDPE (NUPML4E*NPDPEPG)/* number of userland PDP pages */ | * We use the same numbering of the page table pages for 5-level and | ||||
alc: "We use the same numbering ... | |||||
#define NUPDE (NUPDPE*NPDEPG) /* number of userland PD entries */ | * 4-level paging structures. | ||||
*/ | |||||
#define NUPML5E (NPML5EPG / 2) /* number of userland PML5 | |||||
pages */ | |||||
#define NUPML4E (NUPML5E * NPML4EPG) /* number of userland PML4 | |||||
pages */ | |||||
#define NUPDPE (NUPML4E * NPDPEPG) /* number of userland PDP | |||||
pages */ | |||||
#define NUPDE (NUPDPE * NPDEPG) /* number of userland PD | |||||
entries */ | |||||
#define NUP4ML4E (NPML4EPG / 2) | |||||
/* | /* | ||||
* NDMPML4E is the maximum number of PML4 entries that will be | * NDMPML4E is the maximum number of PML4 entries that will be | ||||
* used to implement the direct map. It must be a power of two, | * used to implement the direct map. It must be a power of two, | ||||
* and should generally exceed NKPML4E. The maximum possible | * and should generally exceed NKPML4E. The maximum possible | ||||
* value is 64; using 128 will make the direct map intrude into | * value is 64; using 128 will make the direct map intrude into | ||||
* the recursive page table map. | * the recursive page table map. | ||||
*/ | */ | ||||
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* is 1, these are the same, otherwise KPML4BASE < KPML4I and extra | * is 1, these are the same, otherwise KPML4BASE < KPML4I and extra | ||||
* level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to | * level 4 PDEs are needed to map from VM_MIN_KERNEL_ADDRESS up to | ||||
* KERNBASE. | * KERNBASE. | ||||
* | * | ||||
* (KPML4I combines with KPDPI to choose where KERNBASE starts. | * (KPML4I combines with KPDPI to choose where KERNBASE starts. | ||||
* Or, in other words, KPML4I provides bits 39..47 of KERNBASE, | * Or, in other words, KPML4I provides bits 39..47 of KERNBASE, | ||||
* and KPDPI provides bits 30..38.) | * and KPDPI provides bits 30..38.) | ||||
*/ | */ | ||||
#define PML4PML4I (NPML4EPG/2) /* Index of recursive pml4 mapping */ | #define PML4PML4I (NPML4EPG / 2) /* Index of recursive pml4 mapping */ | ||||
#define PML5PML5I (NPML5EPG / 2) /* Index of recursive pml5 mapping */ | |||||
#define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */ | #define KPML4BASE (NPML4EPG-NKPML4E) /* KVM at highest addresses */ | ||||
#define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */ | #define DMPML4I rounddown(KPML4BASE-NDMPML4E, NDMPML4E) /* Below KVM */ | ||||
#define KPML4I (NPML4EPG-1) | #define KPML4I (NPML4EPG-1) | ||||
#define KPDPI (NPDPEPG-2) /* kernbase at -2GB */ | #define KPDPI (NPDPEPG-2) /* kernbase at -2GB */ | ||||
/* Large map: index of the first and max last pml4 entry */ | /* Large map: index of the first and max last pml4 entry */ | ||||
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#include <sys/_rangeset.h> | #include <sys/_rangeset.h> | ||||
#include <vm/_vm_radix.h> | #include <vm/_vm_radix.h> | ||||
typedef u_int64_t pd_entry_t; | typedef u_int64_t pd_entry_t; | ||||
typedef u_int64_t pt_entry_t; | typedef u_int64_t pt_entry_t; | ||||
typedef u_int64_t pdp_entry_t; | typedef u_int64_t pdp_entry_t; | ||||
typedef u_int64_t pml4_entry_t; | typedef u_int64_t pml4_entry_t; | ||||
typedef u_int64_t pml5_entry_t; | |||||
/* | /* | ||||
* Address of current address space page table maps and directories. | * Address of current address space page table maps and directories. | ||||
*/ | */ | ||||
#ifdef _KERNEL | #ifdef _KERNEL | ||||
#define addr_PTmap (KVADDR(PML4PML4I, 0, 0, 0)) | #define addr_P4Tmap (KV4ADDR(PML4PML4I, 0, 0, 0)) | ||||
#define addr_PDmap (KVADDR(PML4PML4I, PML4PML4I, 0, 0)) | #define addr_P4Dmap (KV4ADDR(PML4PML4I, PML4PML4I, 0, 0)) | ||||
#define addr_PDPmap (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0)) | #define addr_P4DPmap (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, 0)) | ||||
#define addr_PML4map (KVADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I)) | #define addr_P4ML4map (KV4ADDR(PML4PML4I, PML4PML4I, PML4PML4I, PML4PML4I)) | ||||
#define addr_PML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t))) | #define addr_P4ML4pml4e (addr_PML4map + (PML4PML4I * sizeof(pml4_entry_t))) | ||||
#define PTmap ((pt_entry_t *)(addr_PTmap)) | #define P4Tmap ((pt_entry_t *)(addr_P4Tmap)) | ||||
#define PDmap ((pd_entry_t *)(addr_PDmap)) | #define P4Dmap ((pd_entry_t *)(addr_P4Dmap)) | ||||
#define PDPmap ((pd_entry_t *)(addr_PDPmap)) | |||||
#define PML4map ((pd_entry_t *)(addr_PML4map)) | |||||
#define PML4pml4e ((pd_entry_t *)(addr_PML4pml4e)) | |||||
#define addr_P5Tmap (KV5ADDR(PML5PML5I, 0, 0, 0, 0)) | |||||
#define addr_P5Dmap (KV5ADDR(PML5PML5I, PML5PML5I, 0, 0, 0)) | |||||
#define addr_P5DPmap (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, 0, 0)) | |||||
#define addr_P5ML4map (KV5ADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, 0)) | |||||
#define addr_P5ML5map \ | |||||
(KVADDR(PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I, PML5PML5I)) | |||||
#define addr_P5ML5pml5e (addr_P5ML5map + (PML5PML5I * sizeof(pml5_entry_t))) | |||||
#define P5Tmap ((pt_entry_t *)(addr_P5Tmap)) | |||||
#define P5Dmap ((pd_entry_t *)(addr_P5Dmap)) | |||||
extern int nkpt; /* Initial number of kernel page tables */ | extern int nkpt; /* Initial number of kernel page tables */ | ||||
extern u_int64_t KPDPphys; /* physical address of kernel level 3 */ | extern u_int64_t KPDPphys; /* physical address of kernel level 3 */ | ||||
extern u_int64_t KPML4phys; /* physical address of kernel level 4 */ | extern u_int64_t KPML4phys; /* physical address of kernel level 4 */ | ||||
extern u_int64_t KPML5phys; /* physical address of kernel level 5 */ | |||||
/* | /* | ||||
* virtual address to page table entry and | * virtual address to page table entry and | ||||
* to physical address. | * to physical address. | ||||
* Note: these work recursively, thus vtopte of a pte will give | * Note: these work recursively, thus vtopte of a pte will give | ||||
* the corresponding pde that in turn maps it. | * the corresponding pde that in turn maps it. | ||||
*/ | */ | ||||
pt_entry_t *vtopte(vm_offset_t); | pt_entry_t *vtopte(vm_offset_t); | ||||
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}; | }; | ||||
/* | /* | ||||
* The kernel virtual address (KVA) of the level 4 page table page is always | * The kernel virtual address (KVA) of the level 4 page table page is always | ||||
* within the direct map (DMAP) region. | * within the direct map (DMAP) region. | ||||
*/ | */ | ||||
struct pmap { | struct pmap { | ||||
struct mtx pm_mtx; | struct mtx pm_mtx; | ||||
pml4_entry_t *pm_pml4; /* KVA of level 4 page table */ | pml4_entry_t *pm_pmltop; /* KVA of top level page table */ | ||||
pml4_entry_t *pm_pml4u; /* KVA of user l4 page table */ | pml4_entry_t *pm_pmltopu; /* KVA of user top page table */ | ||||
uint64_t pm_cr3; | uint64_t pm_cr3; | ||||
uint64_t pm_ucr3; | uint64_t pm_ucr3; | ||||
TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ | TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ | ||||
cpuset_t pm_active; /* active on cpus */ | cpuset_t pm_active; /* active on cpus */ | ||||
enum pmap_type pm_type; /* regular or nested tables */ | enum pmap_type pm_type; /* regular or nested tables */ | ||||
struct pmap_statistics pm_stats; /* pmap statistics */ | struct pmap_statistics pm_stats; /* pmap statistics */ | ||||
struct vm_radix pm_root; /* spare page table pages */ | struct vm_radix pm_root; /* spare page table pages */ | ||||
long pm_eptgen; /* EPT pmap generation id */ | long pm_eptgen; /* EPT pmap generation id */ | ||||
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void *pmap_mapbios(vm_paddr_t, vm_size_t); | void *pmap_mapbios(vm_paddr_t, vm_size_t); | ||||
void *pmap_mapdev(vm_paddr_t, vm_size_t); | void *pmap_mapdev(vm_paddr_t, vm_size_t); | ||||
void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int); | void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, int); | ||||
void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size); | void *pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size); | ||||
bool pmap_not_in_di(void); | bool pmap_not_in_di(void); | ||||
boolean_t pmap_page_is_mapped(vm_page_t m); | boolean_t pmap_page_is_mapped(vm_page_t m); | ||||
void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); | void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); | ||||
void pmap_pinit_pml4(vm_page_t); | void pmap_pinit_pml4(vm_page_t); | ||||
void pmap_pinit_pml5(vm_page_t); | |||||
bool pmap_ps_enabled(pmap_t pmap); | bool pmap_ps_enabled(pmap_t pmap); | ||||
void pmap_unmapdev(vm_offset_t, vm_size_t); | void pmap_unmapdev(vm_offset_t, vm_size_t); | ||||
void pmap_invalidate_page(pmap_t, vm_offset_t); | void pmap_invalidate_page(pmap_t, vm_offset_t); | ||||
void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t); | void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t); | ||||
void pmap_invalidate_all(pmap_t); | void pmap_invalidate_all(pmap_t); | ||||
void pmap_invalidate_cache(void); | void pmap_invalidate_cache(void); | ||||
void pmap_invalidate_cache_pages(vm_page_t *pages, int count); | void pmap_invalidate_cache_pages(vm_page_t *pages, int count); | ||||
void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); | void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); | ||||
Show All 37 Lines | pmap_pdpe_index(vm_offset_t va) | ||||
return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1)); | return ((va >> PDPSHIFT) & ((1ul << NPDPEPGSHIFT) - 1)); | ||||
} | } | ||||
static __inline vm_pindex_t | static __inline vm_pindex_t | ||||
pmap_pml4e_index(vm_offset_t va) | pmap_pml4e_index(vm_offset_t va) | ||||
{ | { | ||||
return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1)); | return ((va >> PML4SHIFT) & ((1ul << NPML4EPGSHIFT) - 1)); | ||||
} | |||||
static __inline vm_pindex_t | |||||
pmap_pml5e_index(vm_offset_t va) | |||||
{ | |||||
return ((va >> PML5SHIFT) & ((1ul << NPML5EPGSHIFT) - 1)); | |||||
} | } | ||||
#endif /* !LOCORE */ | #endif /* !LOCORE */ | ||||
#endif /* !_MACHINE_PMAP_H_ */ | #endif /* !_MACHINE_PMAP_H_ */ |
"We use the same numbering ...