Differential D26083 Diff 75888 sys/arm64/arm64/hyp_stub.S

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sys/arm64/arm64/hyp_stub.S

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				/*
				* Copyright (c) 2017 Alexandru Elisei <alexandru.elisei@gmail.com>
				* All rights reserved.
				andrewAuthorUnsubmitted Not Done Inline Actions @alexandru.elisei_arm.com Are you happy for me to remove `All rights reserved`? We've been removing them recently as they are no longer needed. andrew: @alexandru.elisei_arm.com Are you happy for me to remove `All rights reserved`? We've been…
				alexandru.elisei_arm.comUnsubmitted Done Inline Actions Sure, please feel free to remove it, from this file, and from any other files where I'm one of the authors. alexandru.elisei_arm.com: Sure, please feel free to remove it, from this file, and from any other files where I'm one of…
				* Copyright (c) 2020 Aandrew Turner
				*
				* This work was supported by Innovate UK project 105694, "Digital Security
				* by Design (DSbD) Technology Platform Prototype".
				*
				* Redistribution and use in source and binary forms, with or without
				* modification, are permitted provided that the following conditions
				* are met:
				* 1. Redistributions of source code must retain the above copyright
				* notice, this list of conditions and the following disclaimer.
				* 2. Redistributions in binary form must reproduce the above copyright
				* notice, this list of conditions and the following disclaimer in the
				* documentation and/or other materials provided with the distribution.
				*
				* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
				* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
				* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
				* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
				* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
				* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
				* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
				* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
				* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
				* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
				* SUCH DAMAGE.
				*/

				#include <machine/asm.h>

				__FBSDID("$FreeBSD$");

				#include <machine/armreg.h>

				.text

				ENTRY(bad_hyp_trap)
				adr x0, .Lbad_hyp_trap_msg
				bl panic
				brk #0
				END(bad_hyp_trap)

				.Lbad_hyp_trap_msg:
				.asciz "Unhandled EL2 exception: %lx %lx %lx"

				.align 3
				.Laddr_bad_hyp_trap:
				.quad bad_hyp_trap

				.macro vector_tail load_esr = 1
				markjUnsubmitted Not Done Inline Actions The argument seems to be unused. markj: The argument seems to be unused.
				markjUnsubmitted Not Done Inline Actions The argument is still there. markj: The argument is still there.
				andrewAuthorUnsubmitted Done Inline Actions It's used in `vector_el1h_sync` andrew: It's used in `vector_el1h_sync`
				.if \load_esr == 1
				mrs x1, esr_el2
				.endif
				mrs x2, elr_el2
				mrs x3, far_el2

				/* Load the bad EL2 trap haandler to return to */
				markjUnsubmitted Not Done Inline Actions Typo, haandler markj: Typo, haandler
				ldr x4, .Laddr_bad_hyp_trap
				msr elr_el2, x4

				ERET
				.endm

				.macro vempty
				.align 7
				vector_tail
				.endm

				.macro vector_el1h_sync
				.align 7

				mrs x1, esr_el2
				/* Extract the EC field from esr_el2 */
				lsr x2, x1, #ESR_ELx_EC_SHIFT
				cmp x2, #EXCP_HVC
				b.ne 1f

				msr vbar_el2, x0
				ERET

				1:
				vector_tail
				.endm

				.text
				.align 11
				.globl hyp_stub_vectors
				hyp_stub_vectors:
				vempty /* Synchronous EL2t */
				vempty /* IRQ EL2t */
				vempty /* FIQ EL2t */
				vempty /* SError EL2t */

				vempty /* Synchronous EL2h */
				vempty /* IRQ EL2h */
				vempty /* FIQ EL2h */
				vempty /* SError EL2h */

				vector_el1h_sync /* Synchronous 64-bit EL1 */
				vempty /* IRQ 64-bit EL1 */
				vempty /* FIQ 64-bit EL1 */
				vempty /* SError 64-bit EL1 */

				vempty /* Synchronous 32-bit EL1 */
				vempty /* IRQ 32-bit EL1 */
				vempty /* FIQ 32-bit EL1 */
				vempty /* SError 32-bit EL1 */