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sys/dev/ixl/i40e_type.h
Show First 20 Lines • Show All 341 Lines • ▼ Show 20 Lines | |||||
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ | #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ | #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ | #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \ | ||||
I40E_PHY_TYPE_OFFSET) | I40E_PHY_TYPE_OFFSET) | ||||
/* Offset for 2.5G/5G PHY Types value to bit number conversion */ | |||||
#define I40E_PHY_TYPE_OFFSET2 (-10) | |||||
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \ | |||||
I40E_PHY_TYPE_OFFSET2) | |||||
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \ | |||||
I40E_PHY_TYPE_OFFSET2) | |||||
#define I40E_HW_CAP_MAX_GPIO 30 | #define I40E_HW_CAP_MAX_GPIO 30 | ||||
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 | #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 | ||||
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 | #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 | ||||
enum i40e_acpi_programming_method { | enum i40e_acpi_programming_method { | ||||
I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, | I40E_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, | ||||
I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 | I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 | ||||
}; | }; | ||||
▲ Show 20 Lines • Show All 1,127 Lines • ▼ Show 20 Lines | struct i40e_hw_port_stats { | ||||
u64 fd_atr_tunnel_match; | u64 fd_atr_tunnel_match; | ||||
u32 fd_atr_status; | u32 fd_atr_status; | ||||
u32 fd_sb_status; | u32 fd_sb_status; | ||||
/* EEE LPI */ | /* EEE LPI */ | ||||
u32 tx_lpi_status; | u32 tx_lpi_status; | ||||
u32 rx_lpi_status; | u32 rx_lpi_status; | ||||
u64 tx_lpi_count; /* etlpic */ | u64 tx_lpi_count; /* etlpic */ | ||||
u64 rx_lpi_count; /* erlpic */ | u64 rx_lpi_count; /* erlpic */ | ||||
u64 tx_lpi_duration; | |||||
u64 rx_lpi_duration; | |||||
}; | }; | ||||
/* Checksum and Shadow RAM pointers */ | /* Checksum and Shadow RAM pointers */ | ||||
#define I40E_SR_NVM_CONTROL_WORD 0x00 | #define I40E_SR_NVM_CONTROL_WORD 0x00 | ||||
#define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 | #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 | ||||
#define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 | #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 | ||||
#define I40E_SR_OPTION_ROM_PTR 0x05 | #define I40E_SR_OPTION_ROM_PTR 0x05 | ||||
#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 | #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 | ||||
Show All 36 Lines | |||||
#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 | #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 | ||||
#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 | #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 | ||||
#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 | #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 | ||||
#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 | #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 | ||||
#define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 | #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 | ||||
#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 | #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 | ||||
#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D | #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D | ||||
#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E | ||||
#define I40E_SR_5TH_FREE_PROVISION_AREA_PTR 0x50 | |||||
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ | /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ | ||||
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 | #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 | ||||
#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 | #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 | ||||
#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 | #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 | ||||
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) | #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) | ||||
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) | #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) | ||||
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) | #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) | ||||
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines | |||||
#define I40E_FLEX_54_SHIFT 9 | #define I40E_FLEX_54_SHIFT 9 | ||||
#define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) | #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT) | ||||
#define I40E_FLEX_55_SHIFT 8 | #define I40E_FLEX_55_SHIFT 8 | ||||
#define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) | #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT) | ||||
#define I40E_FLEX_56_SHIFT 7 | #define I40E_FLEX_56_SHIFT 7 | ||||
#define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) | #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT) | ||||
#define I40E_FLEX_57_SHIFT 6 | #define I40E_FLEX_57_SHIFT 6 | ||||
#define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) | #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT) | ||||
#define I40E_BCM_PHY_PCS_STATUS1_PAGE 0x3 | |||||
#define I40E_BCM_PHY_PCS_STATUS1_REG 0x0001 | |||||
#define I40E_BCM_PHY_PCS_STATUS1_RX_LPI BIT(8) | |||||
#define I40E_BCM_PHY_PCS_STATUS1_TX_LPI BIT(9) | |||||
#endif /* _I40E_TYPE_H_ */ | #endif /* _I40E_TYPE_H_ */ |