Differential D25873 Diff 75331 sys/dev/cxgbe/common/t4_hw.c

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sys/dev/cxgbe/common/t4_hw.c

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Show First 20 Lines • Show All 9,620 Lines • ▼ Show 20 Lines	int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
tpp->tre = G_TIMERRESOLUTION(v);		tpp->tre = G_TIMERRESOLUTION(v);
tpp->dack_re = G_DELAYEDACKRESOLUTION(v);		tpp->dack_re = G_DELAYEDACKRESOLUTION(v);

/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */		/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
for (chan = 0; chan < MAX_NCHAN; chan++)		for (chan = 0; chan < MAX_NCHAN; chan++)
tpp->tx_modq[chan] = chan;		tpp->tx_modq[chan] = chan;

read_filter_mode_and_ingress_config(adap, sleep_ok);		read_filter_mode_and_ingress_config(adap, sleep_ok);

/*
* Cache a mask of the bits that represent the error vector portion of
* rx_pkt.err_vec. T6+ can use a compressed error vector to make room
* for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
*/
tpp->err_vec_mask = htobe16(0xffff);
if (chip_id(adap) > CHELSIO_T5) {		if (chip_id(adap) > CHELSIO_T5) {
		donnerUnsubmitted Done Inline Actions Is this comment outdated? donner: Is this comment outdated?
		npAuthorUnsubmitted Done Inline Actions Yes, it is. I'll get rid of it and mark it done. np: Yes, it is. I'll get rid of it and mark it done.
v = t4_read_reg(adap, A_TP_OUT_CONFIG);		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
if (v & F_CRXPKTENC) {		tpp->rx_pkt_encap = v & F_CRXPKTENC;
tpp->err_vec_mask =		} else
htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));		tpp->rx_pkt_encap = false;
}
}

return 0;		return 0;
}		}

/**		/**
* t4_filter_field_shift - calculate filter field shift		* t4_filter_field_shift - calculate filter field shift
* @adap: the adapter		* @adap: the adapter
* @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)		* @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
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