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sys/x86/iommu/intel_ctx.c
| Show First 20 Lines • Show All 190 Lines • ▼ Show 20 Lines | if ((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) != 0 && | ||||
| KASSERT(domain->pgtbl_obj == NULL, | KASSERT(domain->pgtbl_obj == NULL, | ||||
| ("ctx %p non-null pgtbl_obj", ctx)); | ("ctx %p non-null pgtbl_obj", ctx)); | ||||
| ctx_root = NULL; | ctx_root = NULL; | ||||
| } else { | } else { | ||||
| ctx_root = dmar_pgalloc(domain->pgtbl_obj, 0, | ctx_root = dmar_pgalloc(domain->pgtbl_obj, 0, | ||||
| IOMMU_PGF_NOALLOC); | IOMMU_PGF_NOALLOC); | ||||
| } | } | ||||
| if (dmar_is_buswide_ctx(unit, busno)) { | if (iommu_is_buswide_ctx((struct iommu_unit *)unit, busno)) { | ||||
| MPASS(!move); | MPASS(!move); | ||||
| for (i = 0; i <= PCI_BUSMAX; i++) { | for (i = 0; i <= PCI_BUSMAX; i++) { | ||||
| ctx_id_entry_init_one(&ctxp[i], domain, ctx_root); | ctx_id_entry_init_one(&ctxp[i], domain, ctx_root); | ||||
| } | } | ||||
| } else { | } else { | ||||
| ctx_id_entry_init_one(ctxp, domain, ctx_root); | ctx_id_entry_init_one(ctxp, domain, ctx_root); | ||||
| } | } | ||||
| dmar_flush_ctx_to_ram(unit, ctxp); | dmar_flush_ctx_to_ram(unit, ctxp); | ||||
| ▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines | |||||
| static struct dmar_ctx * | static struct dmar_ctx * | ||||
| dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid, | dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid, | ||||
| int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, | int dev_domain, int dev_busno, const void *dev_path, int dev_path_len, | ||||
| bool id_mapped, bool rmrr_init) | bool id_mapped, bool rmrr_init) | ||||
| { | { | ||||
| struct dmar_domain *domain, *domain1; | struct dmar_domain *domain, *domain1; | ||||
| struct dmar_ctx *ctx, *ctx1; | struct dmar_ctx *ctx, *ctx1; | ||||
| struct iommu_unit *unit; | |||||
| dmar_ctx_entry_t *ctxp; | dmar_ctx_entry_t *ctxp; | ||||
| struct sf_buf *sf; | struct sf_buf *sf; | ||||
| int bus, slot, func, error; | int bus, slot, func, error; | ||||
| bool enable; | bool enable; | ||||
| if (dev != NULL) { | if (dev != NULL) { | ||||
| bus = pci_get_bus(dev); | bus = pci_get_bus(dev); | ||||
| slot = pci_get_slot(dev); | slot = pci_get_slot(dev); | ||||
| func = pci_get_function(dev); | func = pci_get_function(dev); | ||||
| } else { | } else { | ||||
| bus = PCI_RID2BUS(rid); | bus = PCI_RID2BUS(rid); | ||||
| slot = PCI_RID2SLOT(rid); | slot = PCI_RID2SLOT(rid); | ||||
| func = PCI_RID2FUNC(rid); | func = PCI_RID2FUNC(rid); | ||||
| } | } | ||||
| enable = false; | enable = false; | ||||
| TD_PREP_PINNED_ASSERT; | TD_PREP_PINNED_ASSERT; | ||||
| unit = (struct iommu_unit *)dmar; | |||||
| DMAR_LOCK(dmar); | DMAR_LOCK(dmar); | ||||
| KASSERT(!dmar_is_buswide_ctx(dmar, bus) || (slot == 0 && func == 0), | KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0), | ||||
| ("dmar%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus, | ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus, | ||||
| slot, func)); | slot, func)); | ||||
| ctx = dmar_find_ctx_locked(dmar, rid); | ctx = dmar_find_ctx_locked(dmar, rid); | ||||
| error = 0; | error = 0; | ||||
| if (ctx == NULL) { | if (ctx == NULL) { | ||||
| /* | /* | ||||
| * Perform the allocations which require sleep or have | * Perform the allocations which require sleep or have | ||||
| * higher chance to succeed if the sleep is allowed. | * higher chance to succeed if the sleep is allowed. | ||||
| */ | */ | ||||
| ▲ Show 20 Lines • Show All 456 Lines • Show Last 20 Lines | |||||