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head/sys/x86/iommu/intel_drv.c
| Show First 20 Lines • Show All 483 Lines • ▼ Show 20 Lines | dmar_attach(device_t dev) | ||||
| unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + | unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 + | ||||
| DMAR_CTX_CNT), 0, 0, NULL); | DMAR_CTX_CNT), 0, 0, NULL); | ||||
| /* | /* | ||||
| * Allocate and load the root entry table pointer. Enable the | * Allocate and load the root entry table pointer. Enable the | ||||
| * address translation after the required invalidations are | * address translation after the required invalidations are | ||||
| * done. | * done. | ||||
| */ | */ | ||||
| dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO); | dmar_pgalloc(unit->ctx_obj, 0, IOMMU_PGF_WAITOK | IOMMU_PGF_ZERO); | ||||
| DMAR_LOCK(unit); | DMAR_LOCK(unit); | ||||
| error = dmar_load_root_entry_ptr(unit); | error = dmar_load_root_entry_ptr(unit); | ||||
| if (error != 0) { | if (error != 0) { | ||||
| DMAR_UNLOCK(unit); | DMAR_UNLOCK(unit); | ||||
| dmar_release_resources(dev, unit); | dmar_release_resources(dev, unit); | ||||
| return (error); | return (error); | ||||
| } | } | ||||
| error = dmar_inv_ctx_glob(unit); | error = dmar_inv_ctx_glob(unit); | ||||
| ▲ Show 20 Lines • Show All 438 Lines • ▼ Show 20 Lines | if (ptr >= ptrend) | ||||
| break; | break; | ||||
| devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; | devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr; | ||||
| ptr += devscope->Length; | ptr += devscope->Length; | ||||
| match = dmar_match_devscope(devscope, ria->dev_busno, | match = dmar_match_devscope(devscope, ria->dev_busno, | ||||
| ria->dev_path, ria->dev_path_len); | ria->dev_path, ria->dev_path_len); | ||||
| if (match == 1) { | if (match == 1) { | ||||
| entry = iommu_gas_alloc_entry( | entry = iommu_gas_alloc_entry( | ||||
| (struct iommu_domain *)ria->domain, | (struct iommu_domain *)ria->domain, | ||||
| DMAR_PGF_WAITOK); | IOMMU_PGF_WAITOK); | ||||
| entry->start = resmem->BaseAddress; | entry->start = resmem->BaseAddress; | ||||
| /* The RMRR entry end address is inclusive. */ | /* The RMRR entry end address is inclusive. */ | ||||
| entry->end = resmem->EndAddress; | entry->end = resmem->EndAddress; | ||||
| TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, | TAILQ_INSERT_TAIL(ria->rmrr_entries, entry, | ||||
| unroll_link); | unroll_link); | ||||
| } | } | ||||
| } | } | ||||
| ▲ Show 20 Lines • Show All 408 Lines • Show Last 20 Lines | |||||