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sys/amd64/include/param.h
| Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines | |||||
| #define NBPDP (1<<PDPSHIFT) /* bytes/page dir ptr table */ | #define NBPDP (1<<PDPSHIFT) /* bytes/page dir ptr table */ | ||||
| #define PDPMASK (NBPDP-1) | #define PDPMASK (NBPDP-1) | ||||
| /* Size of the level 4 page-map level-4 table units */ | /* Size of the level 4 page-map level-4 table units */ | ||||
| #define NPML4EPG (PAGE_SIZE/(sizeof (pml4_entry_t))) | #define NPML4EPG (PAGE_SIZE/(sizeof (pml4_entry_t))) | ||||
| #define NPML4EPGSHIFT 9 /* LOG2(NPML4EPG) */ | #define NPML4EPGSHIFT 9 /* LOG2(NPML4EPG) */ | ||||
| #define PML4SHIFT 39 /* LOG2(NBPML4) */ | #define PML4SHIFT 39 /* LOG2(NBPML4) */ | ||||
| #define NBPML4 (1UL<<PML4SHIFT)/* bytes/page map lev4 table */ | #define NBPML4 (1UL<<PML4SHIFT)/* bytes/page map lev4 table */ | ||||
| #define PML4MASK (NBPML4-1) | #define PML4MASK (NBPML4-1) | ||||
| /* Size of the level 5 page-map level-5 table units */ | |||||
| #define NPML5EPG (PAGE_SIZE/(sizeof (pml5_entry_t))) | |||||
| #define NPML5EPGSHIFT 9 /* LOG2(NPML5EPG) */ | |||||
| #define PML5SHIFT 48 /* LOG2(NBPML5) */ | |||||
| #define NBPML5 (1UL<<PML5SHIFT)/* bytes/page map lev5 table */ | |||||
| #define PML5MASK (NBPML5-1) | |||||
| #define MAXPAGESIZES 3 /* maximum number of supported page sizes */ | #define MAXPAGESIZES 3 /* maximum number of supported page sizes */ | ||||
| #define IOPAGES 2 /* pages of i/o permission bitmap */ | #define IOPAGES 2 /* pages of i/o permission bitmap */ | ||||
| /* | /* | ||||
| * I/O permission bitmap has a bit for each I/O port plus an additional | * I/O permission bitmap has a bit for each I/O port plus an additional | ||||
| * byte at the end with all bits set. See section "I/O Permission Bit Map" | * byte at the end with all bits set. See section "I/O Permission Bit Map" | ||||
| * in the Intel SDM for more details. | * in the Intel SDM for more details. | ||||
| Show All 33 Lines | |||||