Differential D25672 Diff 74457 sys/x86/iommu/intel_drv.c

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sys/x86/iommu/intel_drv.c

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#define DMAR_FAULT_IRQ_RID 0		#define DMAR_FAULT_IRQ_RID 0
#define DMAR_QI_IRQ_RID 1		#define DMAR_QI_IRQ_RID 1
#define DMAR_REG_RID 2		#define DMAR_REG_RID 2

static devclass_t dmar_devclass;		static devclass_t dmar_devclass;
static device_t *dmar_devs;		static device_t *dmar_devs;
static int dmar_devcnt;		static int dmar_devcnt;
		static bool dmar_running = false;

typedef int (dmar_iter_t)(ACPI_DMAR_HEADER , void *);		typedef int (dmar_iter_t)(ACPI_DMAR_HEADER , void *);

static void		static void
dmar_iterate_tbl(dmar_iter_t iter, void *arg)		dmar_iterate_tbl(dmar_iter_t iter, void *arg)
{		{
ACPI_TABLE_DMAR *dmartbl;		ACPI_TABLE_DMAR *dmartbl;
ACPI_DMAR_HEADER *dmarh;		ACPI_DMAR_HEADER *dmarh;
▲ Show 20 Lines • Show All 445 Lines • ▼ Show 20 Lines	#ifdef NOTYET
if (error != 0) {		if (error != 0) {
DMAR_UNLOCK(unit);		DMAR_UNLOCK(unit);
dmar_release_resources(dev, unit);		dmar_release_resources(dev, unit);
return (error);		return (error);
}		}
DMAR_UNLOCK(unit);		DMAR_UNLOCK(unit);
#endif		#endif

		dmar_running = true;
return (0);		return (0);
}		}

static int		static int
dmar_detach(device_t dev)		dmar_detach(device_t dev)
{		{

return (EBUSY);		return (EBUSY);
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines	dmar_set_buswide_ctx(struct iommu_unit *unit, u_int busno)
MPASS(busno <= PCI_BUSMAX);		MPASS(busno <= PCI_BUSMAX);
DMAR_LOCK(dmar);		DMAR_LOCK(dmar);
dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] \|=		dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] \|=
1 << (busno % (NBBY * sizeof(uint32_t)));		1 << (busno % (NBBY * sizeof(uint32_t)));
DMAR_UNLOCK(dmar);		DMAR_UNLOCK(dmar);
}		}

bool		bool
dmar_is_buswide_ctx(struct dmar_unit *unit, u_int busno)		dmar_is_buswide_ctx(struct iommu_unit *unit, u_int busno)
{		{
		struct dmar_unit *dmar;

		dmar = (struct dmar_unit *)unit;

MPASS(busno <= PCI_BUSMAX);		MPASS(busno <= PCI_BUSMAX);
return ((unit->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &		return ((dmar->buswide_ctxs[busno / NBBY / sizeof(uint32_t)] &
(1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);		(1U << (busno % (NBBY * sizeof(uint32_t))))) != 0);
}		}

static void		static void
dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)		dmar_print_path(int busno, int depth, const ACPI_DMAR_PCI_PATH *path)
{		{
int i;		int i;

▲ Show 20 Lines • Show All 438 Lines • ▼ Show 20 Lines	if (dev == NULL) {
continue;		continue;
iommu_instantiate_ctx(&(iria)->dmar->iommu,		iommu_instantiate_ctx(&(iria)->dmar->iommu,
dev, true);		dev, true);
}		}
}		}

return (1);		return (1);

		}

		int
		dmar_is_running(void)
		{

		return (dmar_running ? 0 : ENXIO);
}		}

/*		/*
* Pre-create all contexts for the DMAR which have RMRR entries.		* Pre-create all contexts for the DMAR which have RMRR entries.
*/		*/
int		int
dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)		dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit)
{		{
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