Differential D25251 Diff 73306 head/sys/dev/mii/brgphyreg.h

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head/sys/dev/mii/brgphyreg.h

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	/*******************************************************/			/*******************************************************/
	/* End: Shared SerDes PHY register definitions */			/* End: Shared SerDes PHY register definitions */
	/*******************************************************/			/*******************************************************/

	/*******************************************************/			/*******************************************************/
	/* Begin: PHY register values for the 5706 PHY */			/* Begin: PHY register values for the 5706 PHY */
	/*******************************************************/			/*******************************************************/

	/*			/*
				* Aux control shadow register, bits 0-2 select function (0x00 to
				* 0x07).
				*/
				#define BRGPHY_AUXCTL_SHADOW_MISC 0x07
				#define BRGPHY_AUXCTL_MISC_DATA_MASK 0x7ff8
				#define BRGPHY_AUXCTL_MISC_READ_SHIFT 12
				#define BRGPHY_AUXCTL_MISC_WRITE_EN 0x8000
				#define BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN 0x0200
				#define BRGPHY_AUXCTL_MISC_WIRESPEED_EN 0x0010

				/*
	* Shadow register 0x1C, bit 15 is write enable,			* Shadow register 0x1C, bit 15 is write enable,
	* bits 14-10 select function (0x00 to 0x1F).			* bits 14-10 select function (0x00 to 0x1F).
	*/			*/
	#define BRGPHY_MII_SHADOW_1C 0x1C			#define BRGPHY_MII_SHADOW_1C 0x1C
	#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000			#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
	#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00			#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
				#define BRGPHY_SHADOW_1C_DATA_MASK 0x03FF

				/* Shadow 0x1C Clock Alignment Control Register (select value 0x03) */
				#define BRGPHY_SHADOW_1C_CLK_CTRL (0x03 << 10)
				#define BRGPHY_SHADOW_1C_GTXCLK_EN 0x0200

	/* Shadow 0x1C Mode Control Register (select value 0x1F) */			/* Shadow 0x1C Mode Control Register (select value 0x1F) */
	#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)			#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
	/* When set, Regs 0-0x0F are 1000X, else 1000T */			/* When set, Regs 0-0x0F are 1000X, else 1000T */
	#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001			#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001

	#define BRGPHY_MII_TEST1 0x1E			#define BRGPHY_MII_TEST1 0x1E
	#define BRGPHY_TEST1_TRIM_EN 0x0010			#define BRGPHY_TEST1_TRIM_EN 0x0010
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