Differential D25098 Diff 73038 head/sys/i386/i386/npx.c

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head/sys/i386/i386/npx.c

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{		{
uint64_t *xstate_bv;		uint64_t *xstate_bv;
register_t saveintr;		register_t saveintr;
int cp[4], i, max_ext_n;		int cp[4], i, max_ext_n;

if (!hw_float)		if (!hw_float)
return;		return;

		/* Do potentially blocking operations before disabling interrupts. */
		fpu_save_area_zone = uma_zcreate("FPU_save_area",
		cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
		XSAVE_AREA_ALIGN - 1, 0);
npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,		npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
M_WAITOK \| M_ZERO);		M_WAITOK \| M_ZERO);
		if (use_xsave) {
		if (xsave_mask >> 32 != 0)
		max_ext_n = fls(xsave_mask >> 32) + 32;
		else
		max_ext_n = fls(xsave_mask);
		xsave_area_desc = malloc(max_ext_n * sizeof(struct
		xsave_area_elm_descr), M_DEVBUF, M_WAITOK \| M_ZERO);
		}

saveintr = intr_disable();		saveintr = intr_disable();
stop_emulating();		stop_emulating();

if (cpu_fxsr)		if (cpu_fxsr)
fpusave_fxsave(npx_initialstate);		fpusave_fxsave(npx_initialstate);
else		else
fpusave_fnsave(npx_initialstate);		fpusave_fnsave(npx_initialstate);
if (cpu_fxsr) {		if (cpu_fxsr) {
Show All 25 Lines	npxinitstate(void *arg __unused)
* Create a table describing the layout of the CPU Extended		* Create a table describing the layout of the CPU Extended
* Save Area.		* Save Area.
*/		*/
if (use_xsave) {		if (use_xsave) {
xstate_bv = (uint64_t )((char )(npx_initialstate + 1) +		xstate_bv = (uint64_t )((char )(npx_initialstate + 1) +
offsetof(struct xstate_hdr, xstate_bv));		offsetof(struct xstate_hdr, xstate_bv));
*xstate_bv = XFEATURE_ENABLED_X87 \| XFEATURE_ENABLED_SSE;		*xstate_bv = XFEATURE_ENABLED_X87 \| XFEATURE_ENABLED_SSE;

if (xsave_mask >> 32 != 0)
max_ext_n = fls(xsave_mask >> 32) + 32;
else
max_ext_n = fls(xsave_mask);
xsave_area_desc = malloc(max_ext_n * sizeof(struct
xsave_area_elm_descr), M_DEVBUF, M_WAITOK \| M_ZERO);
/* x87 state */		/* x87 state */
xsave_area_desc[0].offset = 0;		xsave_area_desc[0].offset = 0;
xsave_area_desc[0].size = 160;		xsave_area_desc[0].size = 160;
/* XMM */		/* XMM */
xsave_area_desc[1].offset = 160;		xsave_area_desc[1].offset = 160;
xsave_area_desc[1].size = 288 - 160;		xsave_area_desc[1].size = 288 - 160;

for (i = 2; i < max_ext_n; i++) {		for (i = 2; i < max_ext_n; i++) {
cpuid_count(0xd, i, cp);		cpuid_count(0xd, i, cp);
xsave_area_desc[i].offset = cp[1];		xsave_area_desc[i].offset = cp[1];
xsave_area_desc[i].size = cp[0];		xsave_area_desc[i].size = cp[0];
}		}
}		}

fpu_save_area_zone = uma_zcreate("FPU_save_area",
cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
XSAVE_AREA_ALIGN - 1, 0);

start_emulating();		start_emulating();
intr_restore(saveintr);		intr_restore(saveintr);
}		}
SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);		SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);

/*		/*
* Free coprocessor (if we have it).		* Free coprocessor (if we have it).
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