Differential D24564 Diff 72892 sys/dev/ixl/i40e_common.c

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sys/dev/ixl/i40e_common.c

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines	if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
case I40E_DEV_ID_QSFP_B:		case I40E_DEV_ID_QSFP_B:
case I40E_DEV_ID_QSFP_C:		case I40E_DEV_ID_QSFP_C:
case I40E_DEV_ID_10G_BASE_T:		case I40E_DEV_ID_10G_BASE_T:
case I40E_DEV_ID_10G_BASE_T4:		case I40E_DEV_ID_10G_BASE_T4:
case I40E_DEV_ID_20G_KR2:		case I40E_DEV_ID_20G_KR2:
case I40E_DEV_ID_20G_KR2_A:		case I40E_DEV_ID_20G_KR2_A:
case I40E_DEV_ID_25G_B:		case I40E_DEV_ID_25G_B:
case I40E_DEV_ID_25G_SFP28:		case I40E_DEV_ID_25G_SFP28:
		case I40E_DEV_ID_X710_N3000:
		case I40E_DEV_ID_XXV710_N3000:
hw->mac.type = I40E_MAC_XL710;		hw->mac.type = I40E_MAC_XL710;
break;		break;
case I40E_DEV_ID_KX_X722:		case I40E_DEV_ID_KX_X722:
case I40E_DEV_ID_QSFP_X722:		case I40E_DEV_ID_QSFP_X722:
case I40E_DEV_ID_SFP_X722:		case I40E_DEV_ID_SFP_X722:
case I40E_DEV_ID_1G_BASE_T_X722:		case I40E_DEV_ID_1G_BASE_T_X722:
case I40E_DEV_ID_10G_BASE_T_X722:		case I40E_DEV_ID_10G_BASE_T_X722:
case I40E_DEV_ID_SFP_I_X722:		case I40E_DEV_ID_SFP_I_X722:
▲ Show 20 Lines • Show All 237 Lines • ▼ Show 20 Lines
* @buf_len: max length of buffer		* @buf_len: max length of buffer
*		*
* Dumps debug log about adminq command with descriptor contents.		* Dumps debug log about adminq command with descriptor contents.
**/		**/
void i40e_debug_aq(struct i40e_hw hw, enum i40e_debug_mask mask, void desc,		void i40e_debug_aq(struct i40e_hw hw, enum i40e_debug_mask mask, void desc,
void *buffer, u16 buf_len)		void *buffer, u16 buf_len)
{		{
struct i40e_aq_desc aq_desc = (struct i40e_aq_desc )desc;		struct i40e_aq_desc aq_desc = (struct i40e_aq_desc )desc;
		u32 effective_mask = hw->debug_mask & mask;
u8 buf = (u8 )buffer;		u8 buf = (u8 )buffer;
u16 len;		u16 len;
u16 i = 0;		u16 i;

if ((!(mask & hw->debug_mask)) \|\| (desc == NULL))		if (!effective_mask \|\| !desc)
return;		return;

len = LE16_TO_CPU(aq_desc->datalen);		len = LE16_TO_CPU(aq_desc->datalen);

i40e_debug(hw, mask,		i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
"AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",		"AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
LE16_TO_CPU(aq_desc->opcode),		LE16_TO_CPU(aq_desc->opcode),
LE16_TO_CPU(aq_desc->flags),		LE16_TO_CPU(aq_desc->flags),
LE16_TO_CPU(aq_desc->datalen),		LE16_TO_CPU(aq_desc->datalen),
LE16_TO_CPU(aq_desc->retval));		LE16_TO_CPU(aq_desc->retval));
i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",		i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
		"\tcookie (h,l) 0x%08X 0x%08X\n",
LE32_TO_CPU(aq_desc->cookie_high),		LE32_TO_CPU(aq_desc->cookie_high),
LE32_TO_CPU(aq_desc->cookie_low));		LE32_TO_CPU(aq_desc->cookie_low));
i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",		i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
		"\tparam (0,1) 0x%08X 0x%08X\n",
LE32_TO_CPU(aq_desc->params.internal.param0),		LE32_TO_CPU(aq_desc->params.internal.param0),
LE32_TO_CPU(aq_desc->params.internal.param1));		LE32_TO_CPU(aq_desc->params.internal.param1));
i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",		i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
		"\taddr (h,l) 0x%08X 0x%08X\n",
LE32_TO_CPU(aq_desc->params.external.addr_high),		LE32_TO_CPU(aq_desc->params.external.addr_high),
LE32_TO_CPU(aq_desc->params.external.addr_low));		LE32_TO_CPU(aq_desc->params.external.addr_low));

if ((buffer != NULL) && (aq_desc->datalen != 0)) {		if (buffer && (buf_len != 0) && (len != 0) &&
		(effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
i40e_debug(hw, mask, "AQ CMD Buffer:\n");		i40e_debug(hw, mask, "AQ CMD Buffer:\n");
if (buf_len < len)		if (buf_len < len)
len = buf_len;		len = buf_len;
/* write the full 16-byte chunks */		/* write the full 16-byte chunks */
for (i = 0; i < (len - 16); i += 16)		for (i = 0; i < (len - 16); i += 16)
i40e_debug(hw, mask,		i40e_debug(hw, mask,
"\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",		"\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
i, buf[i], buf[i+1], buf[i+2], buf[i+3],		i, buf[i], buf[i+1], buf[i+2], buf[i+3],
▲ Show 20 Lines • Show All 650 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>		ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;		I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
func_rid = rd32(hw, I40E_PF_FUNC_RID);		func_rid = rd32(hw, I40E_PF_FUNC_RID);
if (ari)		if (ari)
hw->pf_id = (u8)(func_rid & 0xff);		hw->pf_id = (u8)(func_rid & 0xff);
else		else
hw->pf_id = (u8)(func_rid & 0x7);		hw->pf_id = (u8)(func_rid & 0x7);

if (hw->mac.type == I40E_MAC_X722)		/* NVMUpdate features structure initialization */
hw->flags \|= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE \|		hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;		hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
		hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
		i40e_memset(hw->nvmupd_features.features, 0x0,
		I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
		sizeof(*hw->nvmupd_features.features),
		I40E_NONDMA_MEM);

		/* No features supported at the moment */
		hw->nvmupd_features.features[0] = 0;

status = i40e_init_nvm(hw);		status = i40e_init_nvm(hw);
return status;		return status;
}		}

/**		/**
* i40e_aq_mac_address_read - Retrieve the MAC addresses		* i40e_aq_mac_address_read - Retrieve the MAC addresses
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @flags: a return indicator of what addresses were added to the addr store		* @flags: a return indicator of what addresses were added to the addr store
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines	static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
default:		default:
media = I40E_MEDIA_TYPE_UNKNOWN;		media = I40E_MEDIA_TYPE_UNKNOWN;
break;		break;
}		}

return media;		return media;
}		}

		/**
		* i40e_poll_globr - Poll for Global Reset completion
		* @hw: pointer to the hardware structure
		* @retry_limit: how many times to retry before failure
		**/
		static enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
		u32 retry_limit)
		{
		u32 cnt, reg = 0;

		for (cnt = 0; cnt < retry_limit; cnt++) {
		reg = rd32(hw, I40E_GLGEN_RSTAT);
		if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
		return I40E_SUCCESS;
		i40e_msec_delay(100);
		}

		DEBUGOUT("Global reset failed.\n");
		DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);

		return I40E_ERR_RESET_FAILED;
		}

#define I40E_PF_RESET_WAIT_COUNT 200		#define I40E_PF_RESET_WAIT_COUNT 200
/**		/**
* i40e_pf_reset - Reset the PF		* i40e_pf_reset - Reset the PF
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
*		*
* Assuming someone else has triggered a global reset,		* Assuming someone else has triggered a global reset,
* assure the global reset is complete and then reset the PF		* assure the global reset is complete and then reset the PF
**/		**/
enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)		enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
{		{
u32 cnt = 0;		u32 cnt = 0;
u32 cnt1 = 0;		u32 cnt1 = 0;
u32 reg = 0;		u32 reg = 0;
u32 grst_del;		u32 grst_del;

/* Poll for Global Reset steady state in case of recent GRST.		/* Poll for Global Reset steady state in case of recent GRST.
* The grst delay value is in 100ms units, and we'll wait a		* The grst delay value is in 100ms units, and we'll wait a
* couple counts longer to be sure we don't just miss the end.		* couple counts longer to be sure we don't just miss the end.
*/		*/
grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &		grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>		I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;		I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;

grst_del = grst_del * 20;		grst_del = min(grst_del * 20, 160U);

for (cnt = 0; cnt < grst_del; cnt++) {		for (cnt = 0; cnt < grst_del; cnt++) {
reg = rd32(hw, I40E_GLGEN_RSTAT);		reg = rd32(hw, I40E_GLGEN_RSTAT);
if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))		if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
break;		break;
i40e_msec_delay(100);		i40e_msec_delay(100);
}		}
if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {		if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
Show All 29 Lines	if (!cnt) {
reg = rd32(hw, I40E_PFGEN_CTRL);		reg = rd32(hw, I40E_PFGEN_CTRL);
wr32(hw, I40E_PFGEN_CTRL,		wr32(hw, I40E_PFGEN_CTRL,
(reg \| I40E_PFGEN_CTRL_PFSWR_MASK));		(reg \| I40E_PFGEN_CTRL_PFSWR_MASK));
for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {		for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
reg = rd32(hw, I40E_PFGEN_CTRL);		reg = rd32(hw, I40E_PFGEN_CTRL);
if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))		if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
break;		break;
reg2 = rd32(hw, I40E_GLGEN_RSTAT);		reg2 = rd32(hw, I40E_GLGEN_RSTAT);
if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {		if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");		break;
DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
return I40E_ERR_NOT_READY;
}
i40e_msec_delay(1);		i40e_msec_delay(1);
}		}
if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {		if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
		if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
		return I40E_ERR_RESET_FAILED;
		} else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
DEBUGOUT("PF reset polling failed to complete.\n");		DEBUGOUT("PF reset polling failed to complete.\n");
return I40E_ERR_RESET_FAILED;		return I40E_ERR_RESET_FAILED;
}		}
}		}

i40e_clear_pxe_mode(hw);		i40e_clear_pxe_mode(hw);


▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
*/		*/
static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)		static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
{		{
u32 gpio_val = 0;		u32 gpio_val = 0;
u32 port;		u32 port;

if (!hw->func_caps.led[idx])		if (!hw->func_caps.led[idx])
return 0;		return 0;

gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));		gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>		port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;

/* if PRT_NUM_NA is 1 then this LED is not port specific, OR		/* if PRT_NUM_NA is 1 then this LED is not port specific, OR
* if it is not our port then ignore		* if it is not our port then ignore
*/		*/
if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) \|\|		if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) \|\|
(port != hw->port))		(port != hw->port))
return 0;		return 0;

return gpio_val;		return gpio_val;
}		}

#define I40E_COMBINED_ACTIVITY 0xA		#define I40E_COMBINED_ACTIVITY 0xA
#define I40E_FILTER_ACTIVITY 0xE		#define I40E_FILTER_ACTIVITY 0xE
#define I40E_LINK_ACTIVITY 0xC		#define I40E_LINK_ACTIVITY 0xC
#define I40E_MAC_ACTIVITY 0xD		#define I40E_MAC_ACTIVITY 0xD
		#define I40E_FW_LED BIT(4)
		#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
		I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)

#define I40E_LED0 22		#define I40E_LED0 22

		#define I40E_PIN_FUNC_SDP 0x0
		#define I40E_PIN_FUNC_LED 0x1

/**		/**
* i40e_led_get - return current on/off mode		* i40e_led_get - return current on/off mode
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
*		*
* The value returned is the 'mode' field as defined in the		* The value returned is the 'mode' field as defined in the
* GPIO register definitions: 0x0 = off, 0xf = on, and other		* GPIO register definitions: 0x0 = off, 0xf = on, and other
* values are variations of possible behaviors relating to		* values are variations of possible behaviors relating to
* blink, link, and wire.		* blink, link, and wire.
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
* if this function is used to turn on the blink it should		* if this function is used to turn on the blink it should
* be used to disable the blink when restoring the original state.		* be used to disable the blink when restoring the original state.
**/		**/
void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)		void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
{		{
u32 current_mode = 0;		u32 current_mode = 0;
int i;		int i;

if (mode & 0xfffffff0)		if (mode & ~I40E_LED_MODE_VALID) {
DEBUGOUT1("invalid mode passed in %X\n", mode);		DEBUGOUT1("invalid mode passed in %X\n", mode);
		return;
		}

/* as per the documentation GPIO 22-29 are the LED		/* as per the documentation GPIO 22-29 are the LED
* GPIO pins named LED0..LED7		* GPIO pins named LED0..LED7
*/		*/
for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {		for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
u32 gpio_val = i40e_led_is_mine(hw, i);		u32 gpio_val = i40e_led_is_mine(hw, i);

if (!gpio_val)		if (!gpio_val)
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines	do {

if (report_init)		if (report_init)
desc.params.external.param0 \|=		desc.params.external.param0 \|=
CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);		CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);

status = i40e_asq_send_command(hw, &desc, abilities,		status = i40e_asq_send_command(hw, &desc, abilities,
abilities_size, cmd_details);		abilities_size, cmd_details);

if (status != I40E_SUCCESS)		switch (hw->aq.asq_last_status) {
break;		case I40E_AQ_RC_EIO:

if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
status = I40E_ERR_UNKNOWN_PHY;		status = I40E_ERR_UNKNOWN_PHY;
break;		break;
} else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {		case I40E_AQ_RC_EAGAIN:
i40e_msec_delay(1);		i40e_msec_delay(1);
total_delay++;		total_delay++;
status = I40E_ERR_TIMEOUT;		status = I40E_ERR_TIMEOUT;
		break;
		/* also covers I40E_AQ_RC_OK */
		default:
		break;
}		}
} while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
		} while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
(total_delay < max_delay));		(total_delay < max_delay));

if (status != I40E_SUCCESS)		if (status != I40E_SUCCESS)
return status;		return status;

if (report_init) {		if (report_init) {
if (hw->mac.type == I40E_MAC_XL710 &&		if (hw->mac.type == I40E_MAC_XL710 &&
hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&		hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {		hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines
}		}

/**		/**
* i40e_aq_set_mac_config		* i40e_aq_set_mac_config
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @max_frame_size: Maximum Frame Size to be supported by the port		* @max_frame_size: Maximum Frame Size to be supported by the port
* @crc_en: Tell HW to append a CRC to outgoing frames		* @crc_en: Tell HW to append a CRC to outgoing frames
* @pacing: Pacing configurations		* @pacing: Pacing configurations
		* @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Configure MAC settings for frame size, jumbo frame support and the		* Configure MAC settings for frame size, jumbo frame support and the
* addition of a CRC by the hardware.		* addition of a CRC by the hardware.
**/		**/
enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,		enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
u16 max_frame_size,		u16 max_frame_size,
bool crc_en, u16 pacing,		bool crc_en, u16 pacing,
		bool auto_drop_blocking_packets,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aq_set_mac_config *cmd =		struct i40e_aq_set_mac_config *cmd =
(struct i40e_aq_set_mac_config *)&desc.params.raw;		(struct i40e_aq_set_mac_config *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

if (max_frame_size == 0)		if (max_frame_size == 0)
return I40E_ERR_PARAM;		return I40E_ERR_PARAM;

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_mac_config);		i40e_aqc_opc_set_mac_config);

cmd->max_frame_size = CPU_TO_LE16(max_frame_size);		cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
cmd->params = ((u8)pacing & 0x0F) << 3;		cmd->params = ((u8)pacing & 0x0F) << 3;
if (crc_en)		if (crc_en)
cmd->params \|= I40E_AQ_SET_MAC_CONFIG_CRC_EN;		cmd->params \|= I40E_AQ_SET_MAC_CONFIG_CRC_EN;

		if (auto_drop_blocking_packets) {
		if (hw->flags & I40E_HW_FLAG_DROP_MODE)
		cmd->params \|=
		I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
		else
		i40e_debug(hw, I40E_DEBUG_ALL,
		"This FW api version does not support drop mode.\n");
		}

		#define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
		cmd->fc_refresh_threshold =
		CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_clear_pxe_mode		* i40e_aq_clear_pxe_mode
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
else		else
hw_link_info->lse_enable = FALSE;		hw_link_info->lse_enable = FALSE;

if ((hw->mac.type == I40E_MAC_XL710) &&		if ((hw->mac.type == I40E_MAC_XL710) &&
(hw->aq.fw_maj_ver < 4 \|\| (hw->aq.fw_maj_ver == 4 &&		(hw->aq.fw_maj_ver < 4 \|\| (hw->aq.fw_maj_ver == 4 &&
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)		hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;		hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;

if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&		if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
hw->aq.api_min_ver >= 7) {		hw->mac.type != I40E_MAC_X722) {
__le32 tmp;		__le32 tmp;

i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),		i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
I40E_NONDMA_TO_NONDMA);		I40E_NONDMA_TO_NONDMA);
hw->phy.phy_types = LE32_TO_CPU(tmp);		hw->phy.phy_types = LE32_TO_CPU(tmp);
hw->phy.phy_types \|= ((u64)resp->link_type_ext << 32);		hw->phy.phy_types \|= ((u64)resp->link_type_ext << 32);
}		}

▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);		cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
cmd->connection_type = vsi_ctx->connection_type;		cmd->connection_type = vsi_ctx->connection_type;
cmd->vf_id = vsi_ctx->vf_num;		cmd->vf_id = vsi_ctx->vf_num;
cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);		cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);

desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));

status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,		status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cmd_details);		sizeof(vsi_ctx->info), cmd_details);

if (status != I40E_SUCCESS)		if (status != I40E_SUCCESS)
goto aq_add_vsi_exit;		goto aq_add_vsi_exit;

vsi_ctx->seid = LE16_TO_CPU(resp->seid);		vsi_ctx->seid = LE16_TO_CPU(resp->seid);
vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);		vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);		vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);		vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
▲ Show 20 Lines • Show All 400 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_update_vsi_parameters);		i40e_aqc_opc_update_vsi_parameters);
cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);		cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);

desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));

status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,		status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
sizeof(vsi_ctx->info), cmd_details);		sizeof(vsi_ctx->info), cmd_details);

vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);		vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);		vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);

return status;		return status;
}		}

/**		/**
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&		if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) \|\|		((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) \|\|
!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {		!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
status = i40e_aq_get_phy_capabilities(hw, FALSE, false,		status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
&abilities, NULL);		&abilities, NULL);
if (status)		if (status)
return status;		return status;

		if (abilities.fec_cfg_curr_mod_ext_info &
		I40E_AQ_ENABLE_FEC_AUTO)
hw->phy.link_info.req_fec_info =		hw->phy.link_info.req_fec_info =
		(I40E_AQ_REQUEST_FEC_KR \|
		I40E_AQ_REQUEST_FEC_RS);
		else
		hw->phy.link_info.req_fec_info =
abilities.fec_cfg_curr_mod_ext_info &		abilities.fec_cfg_curr_mod_ext_info &
(I40E_AQ_REQUEST_FEC_KR \| I40E_AQ_REQUEST_FEC_RS);		(I40E_AQ_REQUEST_FEC_KR \|
		I40E_AQ_REQUEST_FEC_RS);

i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,		i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);		sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
}		}
return status;		return status;
}		}


▲ Show 20 Lines • Show All 1,360 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
/* Indirect Command */		/* Indirect Command */
desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
if (buff_size > I40E_AQ_LARGE_BUF)		if (buff_size > I40E_AQ_LARGE_BUF)
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);		desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
desc.datalen = CPU_TO_LE16(buff_size);		desc.datalen = CPU_TO_LE16(buff_size);

cmd->type = mib_type;		cmd->type = mib_type;
cmd->length = CPU_TO_LE16(buff_size);		cmd->length = CPU_TO_LE16(buff_size);
cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));		cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buff));
cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));		cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));

status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);		status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
return status;		return status;
}		}

/**		/**
* i40e_aq_cfg_lldp_mib_change_event		* i40e_aq_cfg_lldp_mib_change_event
Show All 19 Lines	if (!enable_update)
cmd->command \|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;		cmd->command \|= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_add_lldp_tlv		* i40e_aq_restore_lldp
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @bridge_type: type of bridge		* @setting: pointer to factory setting variable or NULL
* @buff: buffer with TLV to add		* @restore: True if factory settings should be restored
* @buff_size: length of the buffer
* @tlv_len: length of the TLV to be added
* @mib_len: length of the LLDP MIB returned in response
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Add the specified TLV to LLDP Local MIB for the given bridge type,		* Restore LLDP Agent factory settings if @restore set to True. In other case
* it is responsibility of the caller to make sure that the TLV is not		* only returns factory setting in AQ response.
* already present in the LLDPDU.
* In return firmware will write the complete LLDP MIB with the newly
* added TLV in the response buffer.
**/		**/
enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,		enum i40e_status_code
void *buff, u16 buff_size, u16 tlv_len,		i40e_aq_restore_lldp(struct i40e_hw hw, u8 setting, bool restore,
u16 *mib_len,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_lldp_add_tlv *cmd =		struct i40e_aqc_lldp_restore *cmd =
(struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;		(struct i40e_aqc_lldp_restore *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

if (buff_size == 0 \|\| !buff \|\| tlv_len == 0)		if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
return I40E_ERR_PARAM;		i40e_debug(hw, I40E_DEBUG_ALL,
		"Restore LLDP not supported by current FW version.\n");
i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);		return I40E_ERR_DEVICE_NOT_SUPPORTED;

/* Indirect Command */
desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
if (buff_size > I40E_AQ_LARGE_BUF)
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
desc.datalen = CPU_TO_LE16(buff_size);

cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
cmd->len = CPU_TO_LE16(tlv_len);

status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
if (!status) {
if (mib_len != NULL)
*mib_len = LE16_TO_CPU(desc.datalen);
}		}

return status;		i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
}

/**		if (restore)
* i40e_aq_update_lldp_tlv		cmd->command \|= I40E_AQ_LLDP_AGENT_RESTORE;
* @hw: pointer to the hw struct
* @bridge_type: type of bridge
* @buff: buffer with TLV to update
* @buff_size: size of the buffer holding original and updated TLVs
* @old_len: Length of the Original TLV
* @new_len: Length of the Updated TLV
* @offset: offset of the updated TLV in the buff
* @mib_len: length of the returned LLDP MIB
* @cmd_details: pointer to command details structure or NULL
*
* Update the specified TLV to the LLDP Local MIB for the given bridge type.
* Firmware will place the complete LLDP MIB in response buffer with the
* updated TLV.
**/
enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
u8 bridge_type, void *buff, u16 buff_size,
u16 old_len, u16 new_len, u16 offset,
u16 *mib_len,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_lldp_update_tlv *cmd =
(struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;
enum i40e_status_code status;

if (buff_size == 0 \|\| !buff \|\| offset == 0 \|\|		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
old_len == 0 \|\| new_len == 0)
return I40E_ERR_PARAM;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);		if (setting)
		*setting = cmd->command & 1;

/* Indirect Command */
desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
if (buff_size > I40E_AQ_LARGE_BUF)
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
desc.datalen = CPU_TO_LE16(buff_size);

cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
cmd->old_len = CPU_TO_LE16(old_len);
cmd->new_offset = CPU_TO_LE16(offset);
cmd->new_len = CPU_TO_LE16(new_len);

status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
if (!status) {
if (mib_len != NULL)
*mib_len = LE16_TO_CPU(desc.datalen);
}

return status;		return status;
}		}

/**		/**
* i40e_aq_delete_lldp_tlv
* @hw: pointer to the hw struct
* @bridge_type: type of bridge
* @buff: pointer to a user supplied buffer that has the TLV
* @buff_size: length of the buffer
* @tlv_len: length of the TLV to be deleted
* @mib_len: length of the returned LLDP MIB
* @cmd_details: pointer to command details structure or NULL
*
* Delete the specified TLV from LLDP Local MIB for the given bridge type.
* The firmware places the entire LLDP MIB in the response buffer.
**/
enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
u8 bridge_type, void *buff, u16 buff_size,
u16 tlv_len, u16 *mib_len,
struct i40e_asq_cmd_details *cmd_details)
{
struct i40e_aq_desc desc;
struct i40e_aqc_lldp_add_tlv *cmd =
(struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;
enum i40e_status_code status;

if (buff_size == 0 \|\| !buff)
return I40E_ERR_PARAM;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);

/* Indirect Command */
desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
if (buff_size > I40E_AQ_LARGE_BUF)
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
desc.datalen = CPU_TO_LE16(buff_size);
cmd->len = CPU_TO_LE16(tlv_len);
cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
I40E_AQ_LLDP_BRIDGE_TYPE_MASK);

status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
if (!status) {
if (mib_len != NULL)
*mib_len = LE16_TO_CPU(desc.datalen);
}

return status;
}

/**
* i40e_aq_stop_lldp		* i40e_aq_stop_lldp
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @shutdown_agent: True if LLDP Agent needs to be Shutdown		* @shutdown_agent: True if LLDP Agent needs to be Shutdown
		* @persist: True if stop of LLDP should be persistent across power cycles
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Stop or Shutdown the embedded LLDP Agent		* Stop or Shutdown the embedded LLDP Agent
**/		**/
enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,		enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
		bool persist,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_lldp_stop *cmd =		struct i40e_aqc_lldp_stop *cmd =
(struct i40e_aqc_lldp_stop *)&desc.params.raw;		(struct i40e_aqc_lldp_stop *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);		i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);

if (shutdown_agent)		if (shutdown_agent)
cmd->command \|= I40E_AQ_LLDP_AGENT_SHUTDOWN;		cmd->command \|= I40E_AQ_LLDP_AGENT_SHUTDOWN;

		if (persist) {
		if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
		cmd->command \|= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
		else
		i40e_debug(hw, I40E_DEBUG_ALL,
		"Persistent Stop LLDP not supported by current FW version.\n");
		}

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_start_lldp		* i40e_aq_start_lldp
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
		* @persist: True if start of LLDP should be persistent across power cycles
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Start the embedded LLDP Agent on all ports.		* Start the embedded LLDP Agent on all ports.
**/		**/
enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,		enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
		bool persist,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_lldp_start *cmd =		struct i40e_aqc_lldp_start *cmd =
(struct i40e_aqc_lldp_start *)&desc.params.raw;		(struct i40e_aqc_lldp_start *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);		i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);

cmd->command = I40E_AQ_LLDP_AGENT_START;		cmd->command = I40E_AQ_LLDP_AGENT_START;

		if (persist) {
		if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
		cmd->command \|= I40E_AQ_LLDP_AGENT_START_PERSIST;
		else
		i40e_debug(hw, I40E_DEBUG_ALL,
		"Persistent Start LLDP not supported by current FW version.\n");
		}

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_set_dcb_parameters		* i40e_aq_set_dcb_parameters
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
* @dcb_enable: True if DCB configuration needs to be applied		* @dcb_enable: True if DCB configuration needs to be applied
*		*
**/		**/
enum i40e_status_code		enum i40e_status_code
i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,		i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_set_dcb_parameters *cmd =		struct i40e_aqc_set_dcb_parameters *cmd =
(struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;		(struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

if ((hw->mac.type != I40E_MAC_XL710) \|\|		if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
((hw->aq.api_maj_ver < 1) \|\|
((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 6))))
return I40E_ERR_DEVICE_NOT_SUPPORTED;		return I40E_ERR_DEVICE_NOT_SUPPORTED;

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_dcb_parameters);		i40e_aqc_opc_set_dcb_parameters);

if (dcb_enable) {		if (dcb_enable) {
cmd->valid_flags = I40E_DCB_VALID;		cmd->valid_flags = I40E_DCB_VALID;
cmd->command = I40E_AQ_DCB_SET_AGENT;		cmd->command = I40E_AQ_DCB_SET_AGENT;
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
enum i40e_status_code status;		enum i40e_status_code status;

if (seid == 0)		if (seid == 0)
return I40E_ERR_PARAM;		return I40E_ERR_PARAM;

i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);		i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);

cmd->seid = CPU_TO_LE16(seid);		cmd->seid = CPU_TO_LE16(seid);

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port		* i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines	enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,
i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_add_multicast_etag);		i40e_aqc_opc_add_multicast_etag);

cmd->pv_seid = CPU_TO_LE16(pv_seid);		cmd->pv_seid = CPU_TO_LE16(pv_seid);
cmd->etag = CPU_TO_LE16(etag);		cmd->etag = CPU_TO_LE16(etag);
cmd->num_unicast_etags = num_tags_in_buf;		cmd->num_unicast_etags = num_tags_in_buf;

desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
if (length > I40E_AQ_LARGE_BUF)
desc.flags \|= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);

status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);		status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);

if (!status) {		if (!status) {
if (tags_used != NULL)		if (tags_used != NULL)
*tags_used = LE16_TO_CPU(resp->mcast_etags_used);		*tags_used = LE16_TO_CPU(resp->mcast_etags_used);
if (tags_free != NULL)		if (tags_free != NULL)
*tags_free = LE16_TO_CPU(resp->mcast_etags_free);		*tags_free = LE16_TO_CPU(resp->mcast_etags_free);
▲ Show 20 Lines • Show All 780 Lines • ▼ Show 20 Lines
* i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue		* i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue
* @filters: list of cloud filters		* @filters: list of cloud filters
* @filter_count: length of list		* @filter_count: length of list
*		*
* There's an issue in the device where the Geneve VNI layout needs		* There's an issue in the device where the Geneve VNI layout needs
* to be shifted 1 byte over from the VxLAN VNI		* to be shifted 1 byte over from the VxLAN VNI
**/		**/
static void i40e_fix_up_geneve_vni(		static void i40e_fix_up_geneve_vni(
struct i40e_aqc_add_remove_cloud_filters_element_data *filters,		struct i40e_aqc_cloud_filters_element_data *filters,
u8 filter_count)		u8 filter_count)
{		{
struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters;		struct i40e_aqc_cloud_filters_element_data *f = filters;
int i;		int i;

for (i = 0; i < filter_count; i++) {		for (i = 0; i < filter_count; i++) {
u16 tnl_type;		u16 tnl_type;
u32 ti;		u32 ti;

tnl_type = (LE16_TO_CPU(f[i].flags) &		tnl_type = (LE16_TO_CPU(f[i].flags) &
I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>		I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;		I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {		if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
ti = LE32_TO_CPU(f[i].tenant_id);		ti = LE32_TO_CPU(f[i].tenant_id);
f[i].tenant_id = CPU_TO_LE32(ti << 8);		f[i].tenant_id = CPU_TO_LE32(ti << 8);
}		}
}		}
}		}

/**		/**
* i40e_aq_add_cloud_filters		* i40e_aq_add_cloud_filters
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @seid: VSI seid to add cloud filters from		* @seid: VSI seid to add cloud filters from
* @filters: Buffer which contains the filters to be added		* @filters: Buffer which contains the filters to be added
* @filter_count: number of filters contained in the buffer		* @filter_count: number of filters contained in the buffer
*		*
* Set the cloud filters for a given VSI. The contents of the		* Set the cloud filters for a given VSI. The contents of the
* i40e_aqc_add_remove_cloud_filters_element_data are filled		* i40e_aqc_cloud_filters_element_data are filled
* in by the caller of the function.		* in by the caller of the function.
*		*
**/		**/
enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,		enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
u16 seid,		u16 seid,
struct i40e_aqc_add_remove_cloud_filters_element_data *filters,		struct i40e_aqc_cloud_filters_element_data *filters,
u8 filter_count)		u8 filter_count)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_add_remove_cloud_filters *cmd =		struct i40e_aqc_add_remove_cloud_filters *cmd =
(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;		(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;
u16 buff_len;		u16 buff_len;

Show All 9 Lines	enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
i40e_fix_up_geneve_vni(filters, filter_count);		i40e_fix_up_geneve_vni(filters, filter_count);

status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);		status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);

return status;		return status;
}		}

/**		/**
* i40e_aq_remove_cloud_filters		* i40e_aq_add_cloud_filters_bb
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
		* @seid: VSI seid to add cloud filters from
		* @filters: Buffer which contains the filters in big buffer to be added
		* @filter_count: number of filters contained in the buffer
		*
		* Set the cloud filters for a given VSI. The contents of the
		* i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
		* the function.
		*
		**/
		enum i40e_status_code
		i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
		struct i40e_aqc_cloud_filters_element_bb *filters,
		u8 filter_count)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_add_remove_cloud_filters *cmd =
		(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
		enum i40e_status_code status;
		u16 buff_len;
		int i;

		i40e_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_add_cloud_filters);

		buff_len = filter_count * sizeof(*filters);
		desc.datalen = CPU_TO_LE16(buff_len);
		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
		cmd->num_filters = filter_count;
		cmd->seid = CPU_TO_LE16(seid);
		cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;

		for (i = 0; i < filter_count; i++) {
		u16 tnl_type;
		u32 ti;

		tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
		I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
		I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;

		/* Due to hardware eccentricities, the VNI for Geneve is shifted
		* one more byte further than normally used for Tenant ID in
		* other tunnel types.
		*/
		if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
		ti = LE32_TO_CPU(filters[i].element.tenant_id);
		filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
		}
		}

		status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);

		return status;
		}

		/**
		* i40e_aq_rem_cloud_filters
		* @hw: pointer to the hardware structure
* @seid: VSI seid to remove cloud filters from		* @seid: VSI seid to remove cloud filters from
* @filters: Buffer which contains the filters to be removed		* @filters: Buffer which contains the filters to be removed
* @filter_count: number of filters contained in the buffer		* @filter_count: number of filters contained in the buffer
*		*
* Remove the cloud filters for a given VSI. The contents of the		* Remove the cloud filters for a given VSI. The contents of the
* i40e_aqc_add_remove_cloud_filters_element_data are filled		* i40e_aqc_cloud_filters_element_data are filled in by the caller
* in by the caller of the function.		* of the function.
*		*
**/		**/
enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,		enum i40e_status_code
u16 seid,		i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
struct i40e_aqc_add_remove_cloud_filters_element_data *filters,		struct i40e_aqc_cloud_filters_element_data *filters,
u8 filter_count)		u8 filter_count)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_add_remove_cloud_filters *cmd =		struct i40e_aqc_add_remove_cloud_filters *cmd =
(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;		(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;
u16 buff_len;		u16 buff_len;

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_remove_cloud_filters);		i40e_aqc_opc_remove_cloud_filters);

buff_len = filter_count * sizeof(*filters);		buff_len = filter_count * sizeof(*filters);
desc.datalen = CPU_TO_LE16(buff_len);		desc.datalen = CPU_TO_LE16(buff_len);
desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
cmd->num_filters = filter_count;		cmd->num_filters = filter_count;
cmd->seid = CPU_TO_LE16(seid);		cmd->seid = CPU_TO_LE16(seid);

i40e_fix_up_geneve_vni(filters, filter_count);		i40e_fix_up_geneve_vni(filters, filter_count);

status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);		status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);

return status;		return status;
}		}

/**		/**
		* i40e_aq_rem_cloud_filters_bb
		* @hw: pointer to the hardware structure
		* @seid: VSI seid to remove cloud filters from
		* @filters: Buffer which contains the filters in big buffer to be removed
		* @filter_count: number of filters contained in the buffer
		*
		* Remove the big buffer cloud filters for a given VSI. The contents of the
		* i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
		* function.
		*
		**/
		enum i40e_status_code
		i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
		struct i40e_aqc_cloud_filters_element_bb *filters,
		u8 filter_count)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_add_remove_cloud_filters *cmd =
		(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
		enum i40e_status_code status;
		u16 buff_len;
		int i;

		i40e_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_remove_cloud_filters);

		buff_len = filter_count * sizeof(*filters);
		desc.datalen = CPU_TO_LE16(buff_len);
		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
		cmd->num_filters = filter_count;
		cmd->seid = CPU_TO_LE16(seid);
		cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;

		for (i = 0; i < filter_count; i++) {
		u16 tnl_type;
		u32 ti;

		tnl_type = (LE16_TO_CPU(filters[i].element.flags) &
		I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
		I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;

		/* Due to hardware eccentricities, the VNI for Geneve is shifted
		* one more byte further than normally used for Tenant ID in
		* other tunnel types.
		*/
		if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
		ti = LE32_TO_CPU(filters[i].element.tenant_id);
		filters[i].element.tenant_id = CPU_TO_LE32(ti << 8);
		}
		}

		status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);

		return status;
		}

		/**
		* i40e_aq_replace_cloud_filters - Replace cloud filter command
		* @hw: pointer to the hw struct
		* @filters: pointer to the i40e_aqc_replace_cloud_filter_cmd struct
		* @cmd_buf: pointer to the i40e_aqc_replace_cloud_filter_cmd_buf struct
		*
		**/
		enum
		i40e_status_code i40e_aq_replace_cloud_filters(struct i40e_hw *hw,
		struct i40e_aqc_replace_cloud_filters_cmd *filters,
		struct i40e_aqc_replace_cloud_filters_cmd_buf *cmd_buf)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_replace_cloud_filters_cmd *cmd =
		(struct i40e_aqc_replace_cloud_filters_cmd *)&desc.params.raw;
		enum i40e_status_code status = I40E_SUCCESS;
		int i = 0;

		/* X722 doesn't support this command */
		if (hw->mac.type == I40E_MAC_X722)
		return I40E_ERR_DEVICE_NOT_SUPPORTED;

		/* need FW version greater than 6.00 */
		if (hw->aq.fw_maj_ver < 6)
		return I40E_NOT_SUPPORTED;

		i40e_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_replace_cloud_filters);

		desc.datalen = CPU_TO_LE16(32);
		desc.flags \|= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD));
		cmd->old_filter_type = filters->old_filter_type;
		cmd->new_filter_type = filters->new_filter_type;
		cmd->valid_flags = filters->valid_flags;
		cmd->tr_bit = filters->tr_bit;
		cmd->tr_bit2 = filters->tr_bit2;

		status = i40e_asq_send_command(hw, &desc, cmd_buf,
		sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf), NULL);

		/* for get cloud filters command */
		for (i = 0; i < 32; i += 4) {
		cmd_buf->filters[i / 4].filter_type = cmd_buf->data[i];
		cmd_buf->filters[i / 4].input[0] = cmd_buf->data[i + 1];
		cmd_buf->filters[i / 4].input[1] = cmd_buf->data[i + 2];
		cmd_buf->filters[i / 4].input[2] = cmd_buf->data[i + 3];
		}

		return status;
		}


		/**
* i40e_aq_alternate_write		* i40e_aq_alternate_write
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @reg_addr0: address of first dword to be read		* @reg_addr0: address of first dword to be read
* @reg_val0: value to be written under 'reg_addr0'		* @reg_val0: value to be written under 'reg_addr0'
* @reg_addr1: address of second dword to be read		* @reg_addr1: address of second dword to be read
* @reg_val1: value to be written under 'reg_addr1'		* @reg_val1: value to be written under 'reg_addr1'
*		*
* Write one or two dwords to alternate structure. Fields are indicated		* Write one or two dwords to alternate structure. Fields are indicated
▲ Show 20 Lines • Show All 805 Lines • ▼ Show 20 Lines
}		}

/**		/**
* i40e_led_get_reg - read LED register		* i40e_led_get_reg - read LED register
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
* @led_addr: LED register address		* @led_addr: LED register address
* @reg_val: read register value		* @reg_val: read register value
**/		**/
static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,		enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
u32 *reg_val)		u32 *reg_val)
{		{
enum i40e_status_code status;		enum i40e_status_code status;
u8 phy_addr = 0;		u8 phy_addr = 0;

*reg_val = 0;		*reg_val = 0;
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {		if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
status = i40e_aq_get_phy_register(hw,		status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,		I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE, TRUE,
I40E_PHY_LED_PROV_REG_1,		I40E_PHY_LED_PROV_REG_1,
reg_val, NULL);		reg_val, NULL);
} else {		} else {
phy_addr = i40e_get_phy_address(hw, hw->port);		phy_addr = i40e_get_phy_address(hw, hw->port);
status = i40e_read_phy_register_clause45(hw,		status = i40e_read_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr,		led_addr, phy_addr,
(u16 *)reg_val);		(u16 *)reg_val);
}		}
return status;		return status;
}		}

/**		/**
* i40e_led_set_reg - write LED register		* i40e_led_set_reg - write LED register
* @hw: pointer to the HW structure		* @hw: pointer to the HW structure
* @led_addr: LED register address		* @led_addr: LED register address
* @reg_val: register value to write		* @reg_val: register value to write
**/		**/
static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,		enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
u32 reg_val)		u32 reg_val)
{		{
enum i40e_status_code status;		enum i40e_status_code status;
u8 phy_addr = 0;		u8 phy_addr = 0;

if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {		if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
status = i40e_aq_set_phy_register(hw,		status = i40e_aq_set_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,		I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE, TRUE,
I40E_PHY_LED_PROV_REG_1,		I40E_PHY_LED_PROV_REG_1,
reg_val, NULL);		reg_val, NULL);
} else {		} else {
phy_addr = i40e_get_phy_address(hw, hw->port);		phy_addr = i40e_get_phy_address(hw, hw->port);
status = i40e_write_phy_register_clause45(hw,		status = i40e_write_phy_register_clause45(hw,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE,
led_addr, phy_addr,		led_addr, phy_addr,
(u16)reg_val);		(u16)reg_val);
Show All 17 Lines	enum i40e_status_code i40e_led_get_phy(struct i40e_hw hw, u16 led_addr,
u32 reg_val_aq;		u32 reg_val_aq;
u16 temp_addr;		u16 temp_addr;
u8 phy_addr = 0;		u8 phy_addr = 0;
u16 reg_val;		u16 reg_val;

if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {		if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
status = i40e_aq_get_phy_register(hw,		status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL,		I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
I40E_PHY_COM_REG_PAGE,		I40E_PHY_COM_REG_PAGE, TRUE,
I40E_PHY_LED_PROV_REG_1,		I40E_PHY_LED_PROV_REG_1,
&reg_val_aq, NULL);		&reg_val_aq, NULL);
if (status == I40E_SUCCESS)		if (status == I40E_SUCCESS)
*val = (u16)reg_val_aq;		*val = (u16)reg_val_aq;
return status;		return status;
}		}
temp_addr = I40E_PHY_LED_PROV_REG_1;		temp_addr = I40E_PHY_LED_PROV_REG_1;
phy_addr = i40e_get_phy_address(hw, hw->port);		phy_addr = i40e_get_phy_address(hw, hw->port);
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines	do_retry:
}		}

/* if the AQ access failed, try the old-fashioned way */		/* if the AQ access failed, try the old-fashioned way */
if (status \|\| use_register)		if (status \|\| use_register)
wr32(hw, reg_addr, reg_val);		wr32(hw, reg_addr, reg_val);
}		}

/**		/**
* i40e_aq_set_phy_register		* i40e_mdio_if_number_selection - MDIO I/F number selection
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
		* @set_mdio: use MDIO I/F number specified by mdio_num
		* @mdio_num: MDIO I/F number
		* @cmd: pointer to PHY Register command structure
		**/
		static void
		i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio, u8 mdio_num,
		struct i40e_aqc_phy_register_access *cmd)
		{
		if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
		if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
		cmd->cmd_flags \|=
		I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER \|
		((mdio_num <<
		I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
		I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
		else
		i40e_debug(hw, I40E_DEBUG_PHY,
		"MDIO I/F number selection not supported by current FW version.\n");
		}
		}

		/**
		* i40e_aq_set_phy_register_ext
		* @hw: pointer to the hw struct
* @phy_select: select which phy should be accessed		* @phy_select: select which phy should be accessed
* @dev_addr: PHY device address		* @dev_addr: PHY device address
		* @page_change: enable auto page change
		* @set_mdio: use MDIO I/F number specified by mdio_num
		* @mdio_num: MDIO I/F number
* @reg_addr: PHY register address		* @reg_addr: PHY register address
* @reg_val: new register value		* @reg_val: new register value
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Write the external PHY register.		* Write the external PHY register.
		* NOTE: In common cases MDIO I/F number should not be changed, thats why you
		* may use simple wrapper i40e_aq_set_phy_register.
**/		**/
enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw,		enum i40e_status_code
u8 phy_select, u8 dev_addr,		i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
		u8 phy_select, u8 dev_addr, bool page_change,
		bool set_mdio, u8 mdio_num,
u32 reg_addr, u32 reg_val,		u32 reg_addr, u32 reg_val,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_phy_register_access *cmd =		struct i40e_aqc_phy_register_access *cmd =
(struct i40e_aqc_phy_register_access *)&desc.params.raw;		(struct i40e_aqc_phy_register_access *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_set_phy_register);		i40e_aqc_opc_set_phy_register);

cmd->phy_interface = phy_select;		cmd->phy_interface = phy_select;
cmd->dev_addres = dev_addr;		cmd->dev_addres = dev_addr;
cmd->reg_address = CPU_TO_LE32(reg_addr);		cmd->reg_address = CPU_TO_LE32(reg_addr);
cmd->reg_value = CPU_TO_LE32(reg_val);		cmd->reg_value = CPU_TO_LE32(reg_val);

		if (!page_change)
		cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;

		i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);

return status;		return status;
}		}

/**		/**
* i40e_aq_get_phy_register		* i40e_aq_get_phy_register_ext
* @hw: pointer to the hw struct		* @hw: pointer to the hw struct
* @phy_select: select which phy should be accessed		* @phy_select: select which phy should be accessed
* @dev_addr: PHY device address		* @dev_addr: PHY device address
		* @page_change: enable auto page change
		* @set_mdio: use MDIO I/F number specified by mdio_num
		* @mdio_num: MDIO I/F number
* @reg_addr: PHY register address		* @reg_addr: PHY register address
* @reg_val: read register value		* @reg_val: read register value
* @cmd_details: pointer to command details structure or NULL		* @cmd_details: pointer to command details structure or NULL
*		*
* Read the external PHY register.		* Read the external PHY register.
		* NOTE: In common cases MDIO I/F number should not be changed, thats why you
		* may use simple wrapper i40e_aq_get_phy_register.
**/		**/
enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw,		enum i40e_status_code
u8 phy_select, u8 dev_addr,		i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
		u8 phy_select, u8 dev_addr, bool page_change,
		bool set_mdio, u8 mdio_num,
u32 reg_addr, u32 *reg_val,		u32 reg_addr, u32 *reg_val,
struct i40e_asq_cmd_details *cmd_details)		struct i40e_asq_cmd_details *cmd_details)
{		{
struct i40e_aq_desc desc;		struct i40e_aq_desc desc;
struct i40e_aqc_phy_register_access *cmd =		struct i40e_aqc_phy_register_access *cmd =
(struct i40e_aqc_phy_register_access *)&desc.params.raw;		(struct i40e_aqc_phy_register_access *)&desc.params.raw;
enum i40e_status_code status;		enum i40e_status_code status;

i40e_fill_default_direct_cmd_desc(&desc,		i40e_fill_default_direct_cmd_desc(&desc,
i40e_aqc_opc_get_phy_register);		i40e_aqc_opc_get_phy_register);

cmd->phy_interface = phy_select;		cmd->phy_interface = phy_select;
cmd->dev_addres = dev_addr;		cmd->dev_addres = dev_addr;
cmd->reg_address = CPU_TO_LE32(reg_addr);		cmd->reg_address = CPU_TO_LE32(reg_addr);

		if (!page_change)
		cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;

		i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);

status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);		status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
if (!status)		if (!status)
*reg_val = LE32_TO_CPU(cmd->reg_value);		*reg_val = LE32_TO_CPU(cmd->reg_value);

return status;		return status;
}		}


/**		/**
* i40e_aq_send_msg_to_pf		* i40e_aq_send_msg_to_pf
* @hw: pointer to the hardware structure		* @hw: pointer to the hardware structure
* @v_opcode: opcodes for VF-PF communication		* @v_opcode: opcodes for VF-PF communication
* @v_retval: return error code		* @v_retval: return error code
* @msg: pointer to the msg buffer		* @msg: pointer to the msg buffer
* @msglen: msg length		* @msglen: msg length
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