Page MenuHomeFreeBSD
Differential D24936 Diff 72051 head/sys/mips/mips/cpu.c

Changeset View

Standalone View

View Options

head/sys/mips/mips/cpu.c

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
#include <machine/regnum.h> #include <machine/regnum.h>
#include <machine/tls.h> #include <machine/tls.h>
#if defined(CPU_CNMIPS) #if defined(CPU_CNMIPS)
#include <contrib/octeon-sdk/cvmx.h> #include <contrib/octeon-sdk/cvmx.h>
#include <contrib/octeon-sdk/octeon-model.h> #include <contrib/octeon-sdk/octeon-model.h>
#endif #endif
static void cpu_identify(void);
struct mips_cpuinfo cpuinfo; struct mips_cpuinfo cpuinfo;
#define _ENCODE_INSN(a,b,c,d,e) \ #define _ENCODE_INSN(a,b,c,d,e) \
((uint32_t)(((a) << 26)|((b) << 21)|((c) << 16)|((d) << 11)|(e))) ((uint32_t)(((a) << 26)|((b) << 21)|((c) << 16)|((d) << 11)|(e)))
#define _JR_RA _ENCODE_INSN(OP_SPECIAL, RA, 0, 0, OP_JR) #define _JR_RA _ENCODE_INSN(OP_SPECIAL, RA, 0, 0, OP_JR)
#define _NOP 0 #define _NOP 0
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Linesmips_cpu_init(void)
mips_wr_wired(0); mips_wr_wired(0);
tlb_invalidate_all(); tlb_invalidate_all();
mips_wr_wired(VMWIRED_ENTRIES); mips_wr_wired(VMWIRED_ENTRIES);
mips_config_cache(&cpuinfo); mips_config_cache(&cpuinfo);
mips_vector_init(); mips_vector_init();
mips_icache_sync_all(); mips_icache_sync_all();
mips_dcache_wbinv_all(); mips_dcache_wbinv_all();
/* Print some info about CPU */
cpu_identify();
} }
static void void
cpu_identify(void) cpu_identify(void)
{ {
uint32_t cfg0, cfg1, cfg2, cfg3; uint32_t cfg0, cfg1, cfg2, cfg3;
#if defined(CPU_MIPS1004K) || defined (CPU_MIPS74K) || defined (CPU_MIPS24K) #if defined(CPU_MIPS1004K) || defined (CPU_MIPS74K) || defined (CPU_MIPS24K)
uint32_t cfg7; uint32_t cfg7;
#endif #endif
printf("cpu%d: ", 0); /* XXX per-cpu */ printf("CPU: ");
switch (cpuinfo.cpu_vendor) { switch (cpuinfo.cpu_vendor) {
case MIPS_PRID_CID_MTI: case MIPS_PRID_CID_MTI:
printf("MIPS Technologies"); printf("MIPS Technologies");
break; break;
case MIPS_PRID_CID_BROADCOM: case MIPS_PRID_CID_BROADCOM:
case MIPS_PRID_CID_SIBYTE: case MIPS_PRID_CID_SIBYTE:
printf("Broadcom"); printf("Broadcom");
break; break;
Show All 25 Lines#endif
case MIPS_PRID_CID_INGENIC2: case MIPS_PRID_CID_INGENIC2:
printf("Ingenic XBurst"); printf("Ingenic XBurst");
break; break;
case MIPS_PRID_CID_PREHISTORIC: case MIPS_PRID_CID_PREHISTORIC:
default: default:
printf("Unknown cid %#x", cpuinfo.cpu_vendor); printf("Unknown cid %#x", cpuinfo.cpu_vendor);
break; break;
} }
if (cpu_model[0] != '\0')
printf(" (%s)", cpu_model);
printf(" processor v%d.%d\n", cpuinfo.cpu_rev, cpuinfo.cpu_impl); printf(" processor v%d.%d\n", cpuinfo.cpu_rev, cpuinfo.cpu_impl);
printf(" MMU: "); printf(" MMU: ");
if (cpuinfo.tlb_type == MIPS_MMU_NONE) { if (cpuinfo.tlb_type == MIPS_MMU_NONE) {
printf("none present\n"); printf("none present\n");
} else { } else {
if (cpuinfo.tlb_type == MIPS_MMU_TLB) { if (cpuinfo.tlb_type == MIPS_MMU_TLB) {
printf("Standard TLB"); printf("Standard TLB");
▲ Show 20 Lines • Show All 234 Lines • Show Last 20 Lines