Differential D24564 Diff 71697 sys/dev/ixl/i40e_register.h

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sys/dev/ixl/i40e_register.h

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	#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)			#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
	#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28			#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28
	#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)			#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
	#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29			#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29
	#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)			#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
	#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30			#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
	#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)			#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
	#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31			#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
	#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)			#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
	#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */			#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
	#define I40E_PF_ARQT_ARQT_SHIFT 0			#define I40E_PF_ARQT_ARQT_SHIFT 0
	#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)			#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
	#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */			#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */
	#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0			#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
	#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)			#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
	#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */			#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */
	#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0			#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
	#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)			#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
	#define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */			#define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */
	#define I40E_PF_ATQH_ATQH_SHIFT 0			#define I40E_PF_ATQH_ATQH_SHIFT 0
	#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)			#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
	#define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */			#define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */
	#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0			#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0
	#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)			#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
	#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28			#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28
	#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)			#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
	#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29			#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29
	#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)			#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
	#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30			#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
	#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)			#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
	#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31			#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
	#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)			#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
	#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */			#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
	#define I40E_PF_ATQT_ATQT_SHIFT 0			#define I40E_PF_ATQT_ATQT_SHIFT 0
	#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)			#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
	#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */			#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	#define I40E_VF_ARQBAH_MAX_INDEX 127			#define I40E_VF_ARQBAH_MAX_INDEX 127
	#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0			#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
	#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)			#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
	#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */			#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
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	#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)			#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
	#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28			#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28
	#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)			#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)
	#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29			#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29
	#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)			#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)
	#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30			#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
	#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)			#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
	#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31			#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
	#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)			#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
	#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */			#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	#define I40E_VF_ARQT_MAX_INDEX 127			#define I40E_VF_ARQT_MAX_INDEX 127
	#define I40E_VF_ARQT_ARQT_SHIFT 0			#define I40E_VF_ARQT_ARQT_SHIFT 0
	#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)			#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
	#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */			#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	#define I40E_VF_ATQBAH_MAX_INDEX 127			#define I40E_VF_ATQBAH_MAX_INDEX 127
	#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0			#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
	#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)			#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
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	#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)			#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
	#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28			#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28
	#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)			#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)
	#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29			#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29
	#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)			#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)
	#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30			#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
	#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)			#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
	#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31			#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
	#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)			#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
	#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */			#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 / / Reset: EMPR */
	#define I40E_VF_ATQT_MAX_INDEX 127			#define I40E_VF_ATQT_MAX_INDEX 127
	#define I40E_VF_ATQT_ATQT_SHIFT 0			#define I40E_VF_ATQT_ATQT_SHIFT 0
	#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)			#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
	#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */			#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */
	#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0			#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
	#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)			#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
	#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */			#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */
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	#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)			#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
	#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 / / Reset: CORER */			#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 / / Reset: CORER */
	#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7			#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7
	#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0			#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0
	#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)			#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
	#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30			#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
	#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)			#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
	#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31			#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
	#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)			#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
	#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */			#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
	#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0			#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
	#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)			#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
	#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8			#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
	#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)			#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
	#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16			#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
	#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)			#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
	#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */			#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */
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	#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)			#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
	#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */			#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */
	#define I40E_GL_FWSTS_FWS0B_SHIFT 0			#define I40E_GL_FWSTS_FWS0B_SHIFT 0
	#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)			#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
	#define I40E_GL_FWSTS_FWRI_SHIFT 9			#define I40E_GL_FWSTS_FWRI_SHIFT 9
	#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)			#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
	#define I40E_GL_FWSTS_FWS1B_SHIFT 16			#define I40E_GL_FWSTS_FWS1B_SHIFT 16
	#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)			#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK \
				I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK \
				I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK \
				I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK \
				I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK \
				I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT)
				#define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK \
				I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT)
	#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */			#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */
	#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0			#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0
	#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)			#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
	#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4			#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4
	#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)			#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
	#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8			#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8
	#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)			#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
	#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12			#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12
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	#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)			#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)
	#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26			#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26
	#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)			#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
	#define I40E_GLGEN_MSCA_STCODE_SHIFT 28			#define I40E_GLGEN_MSCA_STCODE_SHIFT 28
	#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)			#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
	#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30			#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
	#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)			#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
	#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31			#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
	#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)			#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
	#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 / / Reset: POR */			#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 / / Reset: POR */
	#define I40E_GLGEN_MSRWD_MAX_INDEX 3			#define I40E_GLGEN_MSRWD_MAX_INDEX 3
	#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0			#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
	#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)			#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
	#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16			#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
	#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)			#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
	#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */			#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */
	#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0			#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
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	#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11			#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11
	#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0			#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0
	#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)			#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
	#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16			#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16
	#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)			#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)
	#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30			#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
	#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)			#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
	#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31			#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
	#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)			#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
	#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */			#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
	#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0			#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
	#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)			#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
	#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16			#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
	#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)			#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
	#define I40E_PFLAN_QALLOC_VALID_SHIFT 31			#define I40E_PFLAN_QALLOC_VALID_SHIFT 31
	#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)			#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT)
	#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 / / Reset: PFR */			#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 / / Reset: PFR */
	#define I40E_QRX_ENA_MAX_INDEX 1535			#define I40E_QRX_ENA_MAX_INDEX 1535
	#define I40E_QRX_ENA_QENA_REQ_SHIFT 0			#define I40E_QRX_ENA_QENA_REQ_SHIFT 0
	#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)			#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
	#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1			#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1
	#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)			#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)
	#define I40E_QRX_ENA_QENA_STAT_SHIFT 2			#define I40E_QRX_ENA_QENA_STAT_SHIFT 2
	#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)			#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
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	#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)			#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
	#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14			#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14
	#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)			#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)
	#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29			#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29
	#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)			#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)
	#define I40E_GLNVM_SRCTL_START_SHIFT 30			#define I40E_GLNVM_SRCTL_START_SHIFT 30
	#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)			#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
	#define I40E_GLNVM_SRCTL_DONE_SHIFT 31			#define I40E_GLNVM_SRCTL_DONE_SHIFT 31
	#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)			#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT)
	#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */			#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
	#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0			#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
	#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)			#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
	#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16			#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
	#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)			#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
	#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */			#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */
	#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0			#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0
	#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)			#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
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	#define I40E_PF_MDET_TX_VALID_SHIFT 0			#define I40E_PF_MDET_TX_VALID_SHIFT 0
	#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)			#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)
	#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */			#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */
	#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0			#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0
	#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)			#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
	#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8			#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
	#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)			#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
	#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31			#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
	#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)			#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT)
	#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 / / Reset: CORER */			#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 / / Reset: CORER */
	#define I40E_VP_MDET_RX_MAX_INDEX 127			#define I40E_VP_MDET_RX_MAX_INDEX 127
	#define I40E_VP_MDET_RX_VALID_SHIFT 0			#define I40E_VP_MDET_RX_VALID_SHIFT 0
	#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)			#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)
	#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 / / Reset: CORER */			#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 / / Reset: CORER */
	#define I40E_VP_MDET_TX_MAX_INDEX 127			#define I40E_VP_MDET_TX_MAX_INDEX 127
	#define I40E_VP_MDET_TX_VALID_SHIFT 0			#define I40E_VP_MDET_TX_VALID_SHIFT 0
	#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)			#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)
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	#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)			#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
	#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28			#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
	#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)			#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
	#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29			#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
	#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)			#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
	#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30			#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
	#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)			#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
	#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31			#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
	#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)			#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
	#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */			#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
	#define I40E_VF_ARQT1_ARQT_SHIFT 0			#define I40E_VF_ARQT1_ARQT_SHIFT 0
	#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)			#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
	#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */			#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
	#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0			#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
	#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)			#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
	#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */			#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
	#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0			#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
	#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)			#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
	#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */			#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
	#define I40E_VF_ATQH1_ATQH_SHIFT 0			#define I40E_VF_ATQH1_ATQH_SHIFT 0
	#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)			#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
	#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */			#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
	#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0			#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
	#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)			#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
	#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28			#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
	#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)			#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
	#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29			#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
	#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)			#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
	#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30			#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
	#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)			#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
	#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31			#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
	#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)			#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
	#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */			#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
	#define I40E_VF_ATQT1_ATQT_SHIFT 0			#define I40E_VF_ATQT1_ATQT_SHIFT 0
	#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)			#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
	#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */			#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
	#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0			#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
	#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)			#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
	#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */			#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
	#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0			#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
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