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Differential D23731 Diff 71622 head/sys/powerpc/powerpc/trap.c

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head/sys/powerpc/powerpc/trap.c

Show First 20 Lines • Show All 396 Lines • ▼ Show 20 Lines#endif
else if (frame->srr1 & EXC_PGM_ILLEGAL) else if (frame->srr1 & EXC_PGM_ILLEGAL)
ucode = ILL_ILLOPC; ucode = ILL_ILLOPC;
} else if (sig == SIGFPE) } else if (sig == SIGFPE)
ucode = FPE_FLTINV; /* Punt for now, invalid operation. */ ucode = FPE_FLTINV; /* Punt for now, invalid operation. */
} }
break; break;
case EXC_MCHK: case EXC_MCHK:
/* sig = cpu_machine_check(td, frame, &ucode);
* Note that this may not be recoverable for the user printtrap(frame->exc, frame, 0, (frame->srr1 & PSL_PR));
* process, depending on the type of machine check,
* but it at least prevents the kernel from dying.
*/
sig = SIGBUS;
ucode = BUS_OBJERR;
break; break;
#if defined(__powerpc64__) && defined(AIM) #if defined(__powerpc64__) && defined(AIM)
case EXC_SOFT_PATCH: case EXC_SOFT_PATCH:
/* /*
* Point to the instruction that generated the exception to execute it again, * Point to the instruction that generated the exception to execute it again,
* and normalize the register values. * and normalize the register values.
*/ */
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
static void static void
cpu_printtrap(u_int vector, struct trapframe *frame, int isfatal, int user) cpu_printtrap(u_int vector, struct trapframe *frame, int isfatal, int user)
{ {
#ifdef AIM #ifdef AIM
uint16_t ver; uint16_t ver;
switch (vector) { switch (vector) {
case EXC_MCHK:
ver = mfpvr() >> 16;
if (MPC745X_P(ver))
printf(" msssr0 = 0x%b\n",
(int)mfspr(SPR_MSSSR0), MSSSR_BITMASK);
case EXC_DSE: case EXC_DSE:
case EXC_DSI: case EXC_DSI:
case EXC_DTMISS: case EXC_DTMISS:
printf(" dsisr = 0x%lx\n", printf(" dsisr = 0x%lx\n",
(u_long)frame->cpu.aim.dsisr); (u_long)frame->cpu.aim.dsisr);
break; break;
case EXC_MCHK:
ver = mfpvr() >> 16;
if (MPC745X_P(ver))
printf(" msssr0 = 0x%b\n",
(int)mfspr(SPR_MSSSR0), MSSSR_BITMASK);
break;
} }
#elif defined(BOOKE) #elif defined(BOOKE)
vm_paddr_t pa; vm_paddr_t pa;
switch (vector) { switch (vector) {
case EXC_MCHK: case EXC_MCHK:
pa = mfspr(SPR_MCARU); pa = mfspr(SPR_MCARU);
pa = (pa << 32) | (u_register_t)mfspr(SPR_MCAR); pa = (pa << 32) | (u_register_t)mfspr(SPR_MCAR);
Show All 15 Lines printf("%s %s trap:\n", isfatal ? "fatal" : "handled",
user ? "user" : "kernel"); user ? "user" : "kernel");
printf("\n"); printf("\n");
printf(" exception = 0x%x (%s)\n", vector, trapname(vector)); printf(" exception = 0x%x (%s)\n", vector, trapname(vector));
switch (vector) { switch (vector) {
case EXC_DSE: case EXC_DSE:
case EXC_DSI: case EXC_DSI:
case EXC_DTMISS: case EXC_DTMISS:
case EXC_ALI: case EXC_ALI:
case EXC_MCHK:
printf(" virtual address = 0x%" PRIxPTR "\n", frame->dar); printf(" virtual address = 0x%" PRIxPTR "\n", frame->dar);
break; break;
case EXC_ISE: case EXC_ISE:
case EXC_ISI: case EXC_ISI:
case EXC_ITMISS: case EXC_ITMISS:
printf(" virtual address = 0x%" PRIxPTR "\n", frame->srr0); printf(" virtual address = 0x%" PRIxPTR "\n", frame->srr0);
break;
case EXC_MCHK:
break; break;
} }
cpu_printtrap(vector, frame, isfatal, user); cpu_printtrap(vector, frame, isfatal, user);
printf(" srr0 = 0x%" PRIxPTR " (0x%" PRIxPTR ")\n", printf(" srr0 = 0x%" PRIxPTR " (0x%" PRIxPTR ")\n",
frame->srr0, frame->srr0 - (register_t)(__startkernel - KERNBASE)); frame->srr0, frame->srr0 - (register_t)(__startkernel - KERNBASE));
printf(" srr1 = 0x%lx\n", (u_long)frame->srr1); printf(" srr1 = 0x%lx\n", (u_long)frame->srr1);
printf(" current msr = 0x%" PRIxPTR "\n", mfmsr()); printf(" current msr = 0x%" PRIxPTR "\n", mfmsr());
printf(" lr = 0x%" PRIxPTR " (0x%" PRIxPTR ")\n", printf(" lr = 0x%" PRIxPTR " (0x%" PRIxPTR ")\n",
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