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sys/dev/smartpqi/smartpqi_defines.h

/*- /*-
* Copyright (c) 2018 Microsemi Corporation. * Copyright (c) 2016-2019 Microsemi Corporation.
* Copyright (c) 2020 Microchip Technology Inc. and it's subsidiaries.
*
* All rights reserved. * All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
Context not available.
#ifndef _PQI_DEFINES_H #ifndef _PQI_DEFINES_H
#define _PQI_DEFINES_H #define _PQI_DEFINES_H
#define PQI_STATUS_FAILURE -1 #define PQI_STATUS_FAILURE -1
#define PQI_STATUS_TIMEOUT -2 #define PQI_STATUS_TIMEOUT -2
#define PQI_STATUS_QFULL -3 #define PQI_STATUS_QFULL -3
#define PQI_STATUS_SUCCESS 0 #define PQI_STATUS_SUCCESS 0
/* Maximum timeout for internal command completion */
#define TIMEOUT_INFINITE ((uint32_t) (-1))
#define PQISRC_CMD_TIMEOUT TIMEOUT_INFINITE
#define PQISRC_PASSTHROUGH_CMD_TIMEOUT PQISRC_CMD_TIMEOUT
/* Delay in milli seconds */
#define PQISRC_TMF_TIMEOUT (OS_TMF_TIMEOUT_SEC * 1000)
/* Delay in micro seconds */
#define PQISRC_PENDING_IO_TIMEOUT_USEC 30000000 /* 30 seconds */
/* If want to disable atomic operations on device active io, then set to zero */
#define PQISRC_DEVICE_IO_COUNTER 1
#define PQISRC_CMD_TIMEOUT_CNT 1200000 /* 500usec * 1200000 = 5 min */ /* #define SHARE_EVENT_QUEUE_FOR_IO 1 */
#define PQI_CMND_COMPLETE_TMO 1000 /* in millisecond */
#define INVALID_ELEM 0xffff #define INVALID_ELEM 0xffff
#ifndef MIN #ifndef MIN
#define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MIN(a,b) ((a) < (b) ? (a) : (b))
#endif #endif
#ifndef MAX #ifndef MAX
#define MAX(a,b) ((a) > (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b))
#endif #endif
#define PQISRC_ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y)) #define PQISRC_ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y))
#define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) #define PQISRC_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
#define ALIGN_BOUNDARY(a, n) { \ #define ALIGN_BOUNDARY(a, n) { \
if (a % n) \ if (a % n) \
Context not available.
} \ } \
} \ } \
} }
#define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \ #define FILL_QUEUE_ARRAY_ADDR(q,virt,dma) { \
q->array_virt_addr = virt; \ q->array_virt_addr = virt; \
q->array_dma_addr = dma; \ q->array_dma_addr = dma; \
Context not available.
#define false 0 #define false 0
enum INTR_TYPE { enum INTR_TYPE {
LOCK_INTR, LOCK_INTR,
LOCK_SLEEP LOCK_SLEEP
}; };
Context not available.
REQUEST_PENDING = -1, REQUEST_PENDING = -1,
REQUEST_FAILED = -2, REQUEST_FAILED = -2,
}REQUEST_STATUS_T; }REQUEST_STATUS_T;
typedef enum IO_PATH { typedef enum IO_PATH {
AIO_PATH, AIO_PATH,
RAID_PATH RAID_PATH
Context not available.
#define PQI_CTRL_KERNEL_PANIC 0x100 #define PQI_CTRL_KERNEL_PANIC 0x100
#define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF #define SIS_CTL_TO_HOST_DB_DISABLE_ALL 0xFFFFFFFF
#define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000 #define SIS_CTL_TO_HOST_DB_CLEAR 0x00001000
#define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */ #define SIS_CMD_SUBMIT 0x00000200 /* Bit 9 */
#define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */ #define SIS_CMD_COMPLETE 0x00001000 /* Bit 12 */
#define SIS_CMD_STATUS_SUCCESS 0x1 #define SIS_CMD_STATUS_SUCCESS 0x1
/* PQI specific */ /* PQI specific */
Context not available.
#define PQISRC_MAX_SUPPORTED_OP_IB_Q 128 #define PQISRC_MAX_SUPPORTED_OP_IB_Q 128
#define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2) #define PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q (PQISRC_MAX_SUPPORTED_OP_IB_Q / 2)
#define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q) #define PQISRC_MAX_SUPPORTED_OP_AIO_IB_Q (PQISRC_MAX_SUPPORTED_OP_RAID_IB_Q)
#define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q) #define PQISRC_MAX_OP_IB_QUEUE_ELEM_NUM (PQISRC_MAX_OUTSTANDING_REQ / PQISRC_MAX_SUPPORTED_OP_IB_Q)
#define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ #define PQISRC_MAX_OP_OB_QUEUE_ELEM_NUM PQISRC_MAX_OUTSTANDING_REQ
#define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2 #define PQISRC_MIN_OP_OB_QUEUE_ELEM_NUM 2
#define PQISRC_MAX_SUPPORTED_OP_OB_Q 64 #define PQISRC_MAX_SUPPORTED_OP_OB_Q 64
#define PQISRC_OP_MAX_IBQ_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */ #define PQISRC_OP_MAX_IBQ_ELEM_SIZE 8 /* 8 * 16 = 128 bytes */
#define PQISRC_OP_MIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ #define PQISRC_OP_MIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */
#define PQISRC_OP_OBQ_ELEM_SIZE 1 /* 16 bytes */ #define PQISRC_OP_OBQ_ELEM_SIZE 1 /* 16 bytes */
#define PQISRC_ADMIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */ #define PQISRC_ADMIN_IBQ_ELEM_SIZE 2 /* 2 * 16 = 32 bytes */
Context not available.
#define PQISRC_SGL_SUPPORTED_BIT_MASK 0 #define PQISRC_SGL_SUPPORTED_BIT_MASK 0
#define PQISRC_NUM_EVENT_Q_ELEM 32 #define PQISRC_NUM_EVENT_Q_ELEM 32
#define PQISRC_EVENT_Q_ELEM_SIZE 32 #define PQISRC_EVENT_Q_ELEM_SIZE 32
/* PQI Registers state status */ /* PQI Registers state status */
Context not available.
}; };
/* PQI device performing internal initialization (e.g., POST). */ /* PQI device performing internal initialization (e.g., POST). */
#define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0 #define PQI_DEV_STATE_POWER_ON_AND_RESET 0x0
/* Upon entry to this state PQI device initialization begins. */ /* Upon entry to this state PQI device initialization begins. */
#define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1 #define PQI_DEV_STATE_PQI_STATUS_AVAILABLE 0x1
/* PQI device Standard registers are available to the driver. */ /* PQI device Standard registers are available to the driver. */
#define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2 #define PQI_DEV_STATE_ALL_REGISTERS_READY 0x2
/* PQI device is initialized and ready to process any PCI transactions. */ /* PQI device is initialized and ready to process any PCI transactions. */
#define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3 #define PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY 0x3
/* The PQI Device Error register indicates the error. */ /* The PQI Device Error register indicates the error. */
#define PQI_DEV_STATE_ERROR 0x4 #define PQI_DEV_STATE_ERROR 0x4
#define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \ #define PQI_DEV_STATE_AT_INIT ( PQI_DEV_STATE_PQI_STATUS_AVAILABLE | \
PQI_DEV_STATE_ALL_REGISTERS_READY | \ PQI_DEV_STATE_ALL_REGISTERS_READY | \
PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY ) PQI_DEV_STATE_ADMIN_QUEUE_PAIR_READY )
#define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG" #define PQISRC_PQI_DEVICE_SIGNATURE "PQI DREG"
#define PQI_ADMINQ_ELEM_ARRAY_ALIGN 64 #define PQI_ADMINQ_ELEM_ARRAY_ALIGN 64
Context not available.
#define PQI_CONF_TABLE_SIGNATURE "CFGTABLE" #define PQI_CONF_TABLE_SIGNATURE "CFGTABLE"
/* PQI configuration table section IDs */ /* PQI configuration table section IDs */
#define PQI_CONF_TABLE_ALL_SECTIONS (-1)
#define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0 #define PQI_CONF_TABLE_SECTION_GENERAL_INFO 0
#define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1 #define PQI_CONF_TABLE_SECTION_FIRMWARE_FEATURES 1
#define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2 #define PQI_CONF_TABLE_SECTION_FIRMWARE_ERRATA 2
#define PQI_CONF_TABLE_SECTION_DEBUG 3 #define PQI_CONF_TABLE_SECTION_DEBUG 3
#define PQI_CONF_TABLE_SECTION_HEARTBEAT 4 #define PQI_CONF_TABLE_SECTION_HEARTBEAT 4
#define CTRLR_HEARTBEAT_CNT(softs) LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off))
#define PQI_NEW_HEARTBEAT_MECHANISM(softs) 1 #define PQI_FIRMWARE_FEATURE_OFA 0
#define PQI_FIRMWARE_FEATURE_SMP 1
#define PQI_FIRMWARE_FEATURE_MAX_KNOWN 2
#define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_0 3
#define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_1_10 4
#define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_5_50 5
#define PQI_FIRMWARE_FEATURE_AIO_READ_RAID_6_60 6
#define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_0 7
#define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_1_10 8
#define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_5_50 9
#define PQI_FIRMWARE_FEATURE_AIO_WRITE_RAID_6_60 10
#define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE 11
#define PQI_FIRMWARE_FEATURE_SATA_WWN_FOR_DEV_UNIQUE_ID 12
#define PQI_FIRMWARE_FEATURE_TIMEOUT_IN_RAID_IU_SUPPORT 13
#define PQI_FIRMWARE_FEATURE_TIMEOUT_IN_TMF_IU_SUPPORT 14
#define PQI_FIRMWARE_FEATURE_MAXIMUM 14
#define CTRLR_HEARTBEAT_CNT(softs) \
LE_64(PCI_MEM_GET64(softs, softs->heartbeat_counter_abs_addr, softs->heartbeat_counter_off))
#define PQI_HEARTBEAT_TIMEOUT_SEC (10) /* 10 sec interval */
#define PQI_HOST_WELLNESS_TIMEOUT_SEC (24*3600)
/* pqi-2r00a table 36 */ /* pqi-2r00a table 36 */
#define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000) #define PQI_ADMIN_QUEUE_MSIX_DISABLE (0x80000000)
#define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31) #define PQI_ADMIN_QUEUE_MSIX_ENABLE (0 << 31)
#define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01 #define PQI_ADMIN_QUEUE_CONF_FUNC_CREATE_Q_PAIR 0x01
Context not available.
#define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0 #define PQI_IU_TYPE_GENERAL_ADMIN_RESPONSE 0xe0
/* PQI / Vendor specific IU */ /* PQI / Vendor specific IU */
#define PQI_FUNCTION_REPORT_DEV_CAP 0x00 #define PQI_FUNCTION_REPORT_DEV_CAP 0x00
#define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 #define PQI_REQUEST_IU_RAID_TASK_MANAGEMENT 0x13
#define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14 #define PQI_IU_TYPE_RAID_PATH_IO_REQUEST 0x14
#define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15 #define PQI_IU_TYPE_AIO_PATH_IO_REQUEST 0x15
#define PQI_REQUEST_IU_AIO_TASK_MANAGEMENT 0x16
#define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60
#define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72
#define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73
#define PQI_REQUEST_IU_VENDOR_GENERAL 0x75
#define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
#define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93
#define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0
Context not available.
#define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3
#define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4 #define PQI_RESPONSE_IU_AIO_PATH_IS_OFF 0xf4
#define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
#define PQI_RESPONSE_IU_VENDOR_GENERAL 0xf7
#define PQI_REQUEST_HEADER_LENGTH 4 #define PQI_REQUEST_HEADER_LENGTH 4
#define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10 #define PQI_FUNCTION_CREATE_OPERATIONAL_IQ 0x10
#define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11 #define PQI_FUNCTION_CREATE_OPERATIONAL_OQ 0x11
Context not available.
#define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14 #define PQI_FUNCTION_CHANGE_OPERATIONAL_IQ_PROP 0x14
#define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1 #define PQI_CHANGE_OP_IQ_PROP_ASSIGN_AIO 1
#define PQI_DEFAULT_IB_QUEUE 0 #define PQI_DEFAULT_IB_QUEUE 0
#define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
#define PQI_VENDOR_RESPONSE_IU_SUCCESS 0
#define PQI_VENDOR_RESPONSE_IU_UNSUCCESS 1
#define PQI_VENDOR_RESPONSE_IU_INVALID_PARAM 2
#define PQI_VENDOR_RESPONSE_IU_INSUFF_RESRC 3
/* Interface macros */ /* Interface macros */
#define GET_FW_STATUS(softs) \ #define GET_FW_STATUS(softs) \
Context not available.
#define PQI_SAVE_CTRL_MODE(softs, mode) \ #define PQI_SAVE_CTRL_MODE(softs, mode) \
PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode) PCI_MEM_PUT32(softs, &softs->ioa_reg->scratchpad0, LEGACY_SIS_SCR0, mode)
#define PQISRC_MAX_TARGETID 1024 #define PQISRC_MAX_TARGETID 1024
#define PQISRC_MAX_TARGETLUN 64 #define PQISRC_MAX_TARGETLUN 64
/* Vendor specific IU Type for Event config Cmds */ /* Vendor specific IU Type for Event config Cmds */
#define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72 #define PQI_REQUEST_IU_REPORT_EVENT_CONFIG 0x72
#define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73 #define PQI_REQUEST_IU_SET_EVENT_CONFIG 0x73
#define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6
#define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
#define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81
#define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000 #define PQI_MANAGEMENT_CMD_RESP_TIMEOUT 3000
#define PQISRC_EVENT_ACK_RESP_TIMEOUT 1000
/* Supported Event types by controller */ /* Supported Event types by controller */
#define PQI_NUM_SUPPORTED_EVENTS 7
#define PQI_NUM_SUPPORTED_EVENTS 6
#define PQI_EVENT_TYPE_HOTPLUG 0x1 #define PQI_EVENT_TYPE_HOTPLUG 0x1
#define PQI_EVENT_TYPE_HARDWARE 0x2 #define PQI_EVENT_TYPE_HARDWARE 0x2
Context not available.
#define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5
#define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd
#define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe
#define PQI_EVENT_TYPE_HEARTBEAT 0xff
/* for indexing into the pending_events[] field of struct pqisrc_softstate */ /* for indexing into the pending_events[] field of struct pqisrc_softstate */
#define PQI_EVENT_HEARTBEAT 0 #define PQI_EVENT_HOTPLUG 0
#define PQI_EVENT_HOTPLUG 1 #define PQI_EVENT_HARDWARE 1
#define PQI_EVENT_HARDWARE 2 #define PQI_EVENT_PHYSICAL_DEVICE 2
#define PQI_EVENT_PHYSICAL_DEVICE 3 #define PQI_EVENT_LOGICAL_DEVICE 3
#define PQI_EVENT_LOGICAL_DEVICE 4 #define PQI_EVENT_AIO_STATE_CHANGE 4
#define PQI_EVENT_AIO_STATE_CHANGE 5 #define PQI_EVENT_AIO_CONFIG_CHANGE 5
#define PQI_EVENT_AIO_CONFIG_CHANGE 6
#define PQI_MAX_HEARTBEAT_REQUESTS 5
/* Device flags */ /* Device flags */
Context not available.
#define SG_FLAG_LAST 0x40000000 #define SG_FLAG_LAST 0x40000000
#define SG_FLAG_CHAIN 0x80000000 #define SG_FLAG_CHAIN 0x80000000
#define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET) #define IN_PQI_RESET(softs) (softs->ctlr_state & PQI_BUS_RESET)
#define DEV_GONE(dev) (!dev || (dev->invalid == true)) #define DEV_GONE(dev) (!dev || (dev->invalid == true))
#define IS_AIO_PATH(dev) (dev->aio_enabled) #define IS_AIO_PATH(dev) (dev->aio_enabled)
#define IS_RAID_PATH(dev) (!dev->aio_enabled) #define IS_RAID_PATH(dev) (!dev->aio_enabled)
#define DEVICE_RESET(dvp) (dvp->reset_in_progress)
/* SOP data direction flags */ /* SOP data direction flags */
#define SOP_DATA_DIR_NONE 0x00 #define SOP_DATA_DIR_NONE 0x00
#define SOP_DATA_DIR_FROM_DEVICE 0x01 #define SOP_DATA_DIR_FROM_DEVICE 0x01
#define SOP_DATA_DIR_TO_DEVICE 0x02 #define SOP_DATA_DIR_TO_DEVICE 0x02
#define SOP_DATA_DIR_BIDIRECTIONAL 0x03 #define SOP_DATA_DIR_BIDIRECTIONAL 0x03
#define SOP_PARTIAL_DATA_BUFFER 0x04 #define SOP_PARTIAL_DATA_BUFFER 0x04
#define PQISRC_DMA_VALID (1 << 0) #define PQISRC_DMA_VALID (1 << 0)
#define PQISRC_CMD_NO_INTR (1 << 1) #define PQISRC_CMD_NO_INTR (1 << 1)
#define SOP_TASK_ATTRIBUTE_SIMPLE 0 #define SOP_TASK_ATTRIBUTE_SIMPLE 0
#define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1
#define SOP_TASK_ATTRIBUTE_ORDERED 2 #define SOP_TASK_ATTRIBUTE_ORDERED 2
#define SOP_TASK_ATTRIBUTE_ACA 4 #define SOP_TASK_ATTRIBUTE_ACA 4
#define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 #define SOP_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
#define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4 #define SOP_TASK_MANAGEMENT_FUNCTION_REJECTED 0x4
#define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 #define SOP_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
#define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 #define SOP_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
#define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK 0x01
#define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02 #define SOP_TASK_MANAGEMENT_FUNCTION_ABORT_TASK_SET 0x02
#define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8
Context not available.
#define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4
#define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
#define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */ #define PQI_TMF_WAIT_DELAY 10000000 /* 10 seconds */
#define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD #define PQI_RAID_STATUS_GOOD PQI_AIO_STATUS_GOOD
#define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION #define PQI_RAID_STATUS_CHECK_CONDITION PQI_AIO_STATUS_CHECK_CONDITION
#define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET #define PQI_RAID_STATUS_CONDITION_MET PQI_AIO_STATUS_CONDITION_MET
#define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY #define PQI_RAID_STATUS_DEVICE_BUSY PQI_AIO_STATUS_DEVICE_BUSY
#define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD #define PQI_RAID_STATUS_INT_GOOD PQI_AIO_STATUS_INT_GOOD
#define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET #define PQI_RAID_STATUS_INT_COND_MET PQI_AIO_STATUS_INT_COND_MET
#define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT #define PQI_RAID_STATUS_RESERV_CONFLICT PQI_AIO_STATUS_RESERV_CONFLICT
#define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED #define PQI_RAID_STATUS_CMD_TERMINATED PQI_AIO_STATUS_CMD_TERMINATED
#define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL #define PQI_RAID_STATUS_QUEUE_FULL PQI_AIO_STATUS_QUEUE_FULL
#define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED #define PQI_RAID_STATUS_TASK_ABORTED PQI_AIO_STATUS_TASK_ABORTED
#define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN #define PQI_RAID_STATUS_UNDERRUN PQI_AIO_STATUS_UNDERRUN
#define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN #define PQI_RAID_STATUS_OVERRUN PQI_AIO_STATUS_OVERRUN
/* VPD inquiry pages */ /* VPD inquiry pages */
#define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */
#define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */
#define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */ #define SA_VPD_PHYS_DEVICE_ID 0xc0 /* vendor-specific page */
#define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ #define SA_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */
#define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */ #define SA_VPD_LV_IOACCEL_STATUS 0xc2 /* vendor-specific page */
#define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */ #define SA_VPD_LV_STATUS 0xc3 /* vendor-specific page */
#define VPD_PAGE (1 << 8) #define VPD_PAGE (1 << 8)
/* logical volume states */ /* logical volume states */
Context not available.
/* 0 = no limit */ /* 0 = no limit */
#define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0 #define PQI_LOGICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 0
#define PQI_LOG_EXT_QUEUE_DEPTH_ENABLED 0x20
#define PQI_LOG_EXT_QUEUE_ENABLE 0x56
#define MAX_RAW_M256_QDEPTH 32512
#define MAX_RAW_M16_QDEPTH 2032
#define PQI_PTRAID_UPDATE_ON_RESCAN_LUNS 0x80000000
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
Context not available.
#define SA_CISS_READ 0xc0 #define SA_CISS_READ 0xc0
#define SA_GET_RAID_MAP 0xc8 #define SA_GET_RAID_MAP 0xc8
#define SA_REPORT_LOG_EXTENDED 0x1 #define SCSI_SENSE_RESPONSE_70 0x70
#define SA_REPORT_PHYS_EXTENDED 0x2 #define SCSI_SENSE_RESPONSE_71 0x71
#define SCSI_SENSE_RESPONSE_72 0x72
#define SCSI_SENSE_RESPONSE_73 0x73
#define SA_CACHE_FLUSH_BUF_LEN 4 #define SA_REPORT_LOG_EXTENDED 0x1
#define SA_REPORT_PHYS_EXTENDED 0x2
#define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8 #define SA_CACHE_FLUSH_BUF_LEN 4
#define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U)
#define RAID_MAP_MAX_ENTRIES 1024 #define GET_SCSI_SNO(cmd) (cmd->cmdId.serialNumber)
#define RAID_MAP_ENCRYPTION_ENABLED 0x1
#define REPORT_LUN_DEV_FLAG_AIO_ENABLED 0x8
#define PQI_MAX_TRANSFER_SIZE (4 * 1024U * 1024U)
#define RAID_MAP_MAX_ENTRIES 1024
#define RAID_MAP_ENCRYPTION_ENABLED 0x1
#define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27
#define ASC_LUN_NOT_READY 0x4 #define ASC_LUN_NOT_READY 0x4
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#define OFFLOAD_CONFIGURED_BIT 0x1 #define OFFLOAD_CONFIGURED_BIT 0x1
#define OFFLOAD_ENABLED_BIT 0x2 #define OFFLOAD_ENABLED_BIT 0x2
#define PQI_RAID_DATA_IN_OUT_GOOD 0x0 #define PQI_RAID_DATA_IN_OUT_GOOD 0x0
#define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1 #define PQI_RAID_DATA_IN_OUT_UNDERFLOW 0x1
#define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 #define PQI_RAID_DATA_IN_OUT_BUFFER_ERROR 0x40
#define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4 #define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW 0x41
#define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42
#define PQI_RAID_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43
#define PQI_RAID_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60
#define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61
#define PQI_RAID_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62
#define PQI_RAID_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x63
#define PQI_RAID_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64
#define PQI_RAID_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65
#define PQI_RAID_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66
#define PQI_RAID_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67
#define PQI_RAID_DATA_IN_OUT_ERROR 0xf0
#define PQI_RAID_DATA_IN_OUT_PROTOCOL_ERROR 0xf1
#define PQI_RAID_DATA_IN_OUT_HARDWARE_ERROR 0xf2
#define PQI_RAID_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3
#define PQI_RAID_DATA_IN_OUT_ABORTED 0xf4
#define PQI_RAID_DATA_IN_OUT_TIMEOUT 0xf5
#define PQI_PHYSICAL_DEVICE_BUS 0 #define PQI_PHYSICAL_DEVICE_BUS 0
#define PQI_RAID_VOLUME_BUS 1 #define PQI_RAID_VOLUME_BUS 1
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#define SA_RAID_MAX SA_RAID_ADM #define SA_RAID_MAX SA_RAID_ADM
#define SA_RAID_UNKNOWN 0xff #define SA_RAID_UNKNOWN 0xff
#define BIT0 (1 << 0)
#define BIT1 (1 << 1)
#define BIT2 (1 << 2)
#define BIT3 (1 << 3)
#define BITS_PER_BYTE 8
/* BMIC commands */ /* BMIC commands */
#define BMIC_IDENTIFY_CONTROLLER 0x11 #define BMIC_IDENTIFY_CONTROLLER 0x11
#define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15
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#define BMIC_CACHE_FLUSH 0xc2 #define BMIC_CACHE_FLUSH 0xc2
#define BMIC_FLASH_FIRMWARE 0xf7 #define BMIC_FLASH_FIRMWARE 0xf7
#define BMIC_WRITE_HOST_WELLNESS 0xa5 #define BMIC_WRITE_HOST_WELLNESS 0xa5
#define BMIC_SET_DIAGS_OPTIONS 0xf4
#define BMIC_SENSE_DIAGS_OPTIONS 0xf5
#define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0) #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xC0)
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PQI_RESERVED_IO_SLOTS_TMF + \ PQI_RESERVED_IO_SLOTS_TMF + \
PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS) PQI_RESERVED_IO_SLOTS_SYNC_REQUESTS)
/* Defines for print flags */
#define PRINT_FLAG_HDR_COLUMN 0x0001
static inline uint16_t GET_LE16(const uint8_t *p) static inline uint16_t GET_LE16(const uint8_t *p)
{ {
return p[0] | p[1] << 8; return p[0] | p[1] << 8;
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PUT_BE32(val, p + 4); PUT_BE32(val, p + 4);
} }
#define OS_FREEBSD #define OS_FREEBSD
#define SIS_POLL_WAIT #define SIS_POLL_WAIT
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#define PQISRC_DRIVER_MAJOR 1 #define PQISRC_DRIVER_MAJOR 1
#define PQISRC_DRIVER_MINOR 0 #define PQISRC_DRIVER_MINOR 0
#define PQISRC_DRIVER_RELEASE 3 #define PQISRC_DRIVER_RELEASE 4
#define PQISRC_DRIVER_REVISION 239 #define PQISRC_DRIVER_REVISION 215
#define STR(s) # s #define STR(s) # s
#define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d) #define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d)
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#undef ASSERT #undef ASSERT
#endif #endif
/*
*os_atomic64_cas--
*
*Atomically read, compare, and conditionally write.
*i.e. compare and swap.
*retval True On Success
*retval False On Failure
*
*/
static inline boolean_t
os_atomic64_cas(volatile uint64_t* var, uint64_t old_val, uint64_t new_val)
{
return (atomic_cmpset_64(var, old_val, new_val));
}
#define ASSERT(cond) {\ #define ASSERT(cond) {\
if (!(cond)) { \ if (!(cond)) { \
printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \ printf("Assertion failed at file %s line %d\n",__FILE__,__LINE__); \
} \ } \
} }
/* Atomic */
typedef volatile uint64_t OS_ATOMIC64_T;
#define OS_ATOMIC64_READ(p) atomic_load_acq_64(p)
#define OS_ATOMIC64_INIT(p,val) atomic_store_rel_64(p, val)
/* 64-bit post atomic increment and decrement operations on value in pointer.*/
#define OS_ATOMIC64_DEC(p) (atomic_fetchadd_64(p, -1) - 1)
#define OS_ATOMIC64_INC(p) (atomic_fetchadd_64(p, 1) + 1)
#define PQI_MAX_MSIX 64 /* vectors */ #define PQI_MAX_MSIX 64 /* vectors */
#define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1 #define PQI_MSI_CTX_SIZE sizeof(pqi_intr_ctx)+1
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#define OS_SLEEP(timeout) \ #define OS_SLEEP(timeout) \
DELAY(timeout); DELAY(timeout);
#define OS_HOST_WELLNESS_TIMEOUT (24 * 3600) /* TMF request timeout is 600 Sec */
#define OS_TMF_TIMEOUT_SEC (10 * 60)
#define LE_16(x) htole16(x) #define LE_16(x) htole16(x)
#define LE_32(x) htole32(x) #define LE_32(x) htole32(x)
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struct cam_path *path; struct cam_path *path;
struct task event_task; struct task event_task;
struct cdev *cdev; struct cdev *cdev;
struct callout wellness_periodic; /* periodic event handling */ struct callout wellness_periodic; /* periodic event handling */
struct callout heartbeat_timeout_id; /* heart beat event handling */ struct callout heartbeat_timeout_id; /* heart beat event handling */
eventhandler_tag eh;
} OS_SPECIFIC_T; } OS_SPECIFIC_T;
typedef bus_addr_t dma_addr_t; typedef bus_addr_t dma_addr_t;
/* Atomic */
typedef volatile uint64_t OS_ATOMIC64_T;
#define OS_ATOMIC64_SET(_softs, target, val) atomic_set_long(&(_softs)->target, val)
#define OS_ATOMIC64_READ(_softs, target) atomic_load_acq_64(&(_softs)->target)
#define OS_ATOMIC64_INC(_softs, target) atomic_add_64(&(_softs)->target, 1)
/* Register access macros */ /* Register access macros */
#define PCI_MEM_GET32( _softs, _absaddr, _offset ) \ #define PCI_MEM_GET32( _softs, _absaddr, _offset ) \
bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \ bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset) _softs->pci_mem_handle.pqi_bhandle, _offset)
#define PCI_MEM_GET64( _softs, _absaddr, _offset ) \
bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \ #if defined(__i386__)
_softs->pci_mem_handle.pqi_bhandle, _offset) #define PCI_MEM_GET64( _softs, _absaddr, _offset ) ({ \
(uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset) + \
((uint64_t)bus_space_read_4(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset + 4) << 32); \
})
#else
#define PCI_MEM_GET64(_softs, _absaddr, _offset ) \
bus_space_read_8(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset)
#endif
#define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \ #define PCI_MEM_PUT32( _softs, _absaddr, _offset, _val ) \
bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \ bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset, _val) _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
#if defined(__i386__)
#define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset, _val); \
bus_space_write_4(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset + 4, _val >> 32);
#else
#define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \ #define PCI_MEM_PUT64( _softs, _absaddr, _offset, _val ) \
bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \ bus_space_write_8(_softs->pci_mem_handle.pqi_btag, \
_softs->pci_mem_handle.pqi_bhandle, _offset, _val) _softs->pci_mem_handle.pqi_bhandle, _offset, _val)
#endif
#define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \ #define PCI_MEM_GET_BUF(_softs, _absaddr, _offset, buf, size) \
bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\ bus_space_read_region_1(_softs->pci_mem_handle.pqi_btag,\
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typedef struct mtx OS_LOCK_T; typedef struct mtx OS_LOCK_T;
typedef struct sema OS_SEMA_LOCK_T; typedef struct sema OS_SEMA_LOCK_T;
#define OS_PQILOCK_T OS_LOCK_T #define OS_PQILOCK_T OS_LOCK_T
#define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock) #define OS_ACQUIRE_SPINLOCK(_lock) mtx_lock_spin(_lock)
#define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock) #define OS_RELEASE_SPINLOCK(_lock) mtx_unlock_spin(_lock)
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#define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock) #define PQI_LOCK(_lock) OS_ACQUIRE_SPINLOCK(_lock)
#define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock) #define PQI_UNLOCK(_lock) OS_RELEASE_SPINLOCK(_lock)
#define OS_GET_CDBP(rcb) ((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes) #define OS_GET_CDBP(rcb) \
((rcb->cm_ccb->ccb_h.flags & CAM_CDB_POINTER) ? rcb->cm_ccb->csio.cdb_io.cdb_ptr : rcb->cm_ccb->csio.cdb_io.cdb_bytes)
#define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len) #define GET_SCSI_BUFFLEN(rcb) (rcb->cm_ccb->csio.dxfer_len)
#define IS_OS_SCSICMD(rcb) (rcb && !rcb->tm_req && rcb->cm_ccb)
#define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq #define OS_GET_IO_QINDEX(softs,rcb) curcpu % softs->num_op_obq
#define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id) #define OS_GET_IO_RESP_QID(softs,rcb) (softs->op_ob_q[(OS_GET_IO_QINDEX(softs,rcb))].q_id)
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#define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX #define OS_GET_TMF_REQ_QINDEX OS_GET_IO_REQ_QINDEX
/* check request type */ /* check request type */
#define is_internal_req(rcb) (!(rcb)->cm_ccb) #define is_internal_req(rcb) (!(rcb->cm_ccb))
#define os_io_memcpy(dest, src, len) memcpy(dest, src, len)
/* sg elements addr, len, flags */ /* sg elements addr, len, flags */
#define OS_GET_IO_SG_COUNT(rcb) rcb->nseg #define OS_GET_IO_SG_COUNT(rcb) rcb->nseg
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#define SCMD_READ_16 READ_16 #define SCMD_READ_16 READ_16
#define SCMD_WRITE_16 WRITE_16 #define SCMD_WRITE_16 WRITE_16
/* FreeBSD status macros */
#define BSD_FAILURE -1
#define BSD_SUCCESS 0
/* Debug facility */ /* Debug facility */
#define PQISRC_LOG_LEVEL 0x60 #define PQISRC_LOG_LEVEL 0x60
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#define PQISRC_FLAGS_DISC 0x00000010 #define PQISRC_FLAGS_DISC 0x00000010
#define PQISRC_FLAGS_WARN 0x00000020 #define PQISRC_FLAGS_WARN 0x00000020
#define PQISRC_FLAGS_ERROR 0x00000040 #define PQISRC_FLAGS_ERROR 0x00000040
#define PQISRC_FLAGS_NOTE 0x00000080
#define DBG_INIT(fmt,args...) \ #define DBG_INIT(fmt,args...) \
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} \ } \
}while(0); }while(0);
#endif // _PQI_DEFINES_H #define DBG_NOTE(fmt,args...) \
do { \
if (logging_level & PQISRC_FLAGS_NOTE) { \
printf("[INFO]:[ %s ] [ %d ]"fmt,__func__,__LINE__,##args); \
} \
}while(0);
#endif /* _PQI_DEFINES_H */
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