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Differential D24564 Diff 71356 sys/dev/ixl/ixl_pf_i2c.c

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sys/dev/ixl/ixl_pf_i2c.c

Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lineswrite_byte_out:
i2cctl &= ~I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK; i2cctl &= ~I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK;
wr32(hw, IXL_I2C_REG(hw), i2cctl); wr32(hw, IXL_I2C_REG(hw), i2cctl);
ixl_flush(hw); ixl_flush(hw);
return status; return status;
} }
/** /**
* ixl_read_i2c_byte - Reads 8 bit word over I2C using a hardware register * ixl_read_i2c_byte_reg - Reads 8 bit word over I2C using a hardware register
**/ **/
s32 s32
ixl_read_i2c_byte_reg(struct ixl_pf *pf, u8 byte_offset, ixl_read_i2c_byte_reg(struct ixl_pf *pf, u8 byte_offset,
u8 dev_addr, u8 *data) u8 dev_addr, u8 *data)
{ {
struct i40e_hw *hw = &pf->hw; struct i40e_hw *hw = &pf->hw;
u32 reg = 0; u32 reg = 0;
s32 status; s32 status;
*data = 0; *data = 0;
reg |= (byte_offset << I40E_GLGEN_I2CCMD_REGADD_SHIFT); reg |= (byte_offset << I40E_GLGEN_I2CCMD_REGADD_SHIFT);
reg |= (((dev_addr >> 1) & 0x7) << I40E_GLGEN_I2CCMD_PHYADD_SHIFT); reg |= (((dev_addr >> 1) & 0x7) << I40E_GLGEN_I2CCMD_PHYADD_SHIFT);
reg |= I40E_GLGEN_I2CCMD_OP_MASK; reg |= I40E_GLGEN_I2CCMD_OP_MASK;
wr32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num), reg); wr32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num), reg);
status = ixl_wait_for_i2c_completion(hw, hw->func_caps.mdio_port_num); status = ixl_wait_for_i2c_completion(hw, hw->func_caps.mdio_port_num);
/* Get data from I2C register */ /* Get data from I2C register */
reg = rd32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num)); reg = rd32(hw, I40E_GLGEN_I2CCMD(hw->func_caps.mdio_port_num));
/* Retrieve data readed from EEPROM */ /* Retrieve data read from EEPROM */
*data = (u8)(reg & 0xff); *data = (u8)(reg & 0xff);
if (status) if (status)
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read error\n"); ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read error\n");
return status; return status;
} }
/** /**
* ixl_write_i2c_byte - Writes 8 bit word over I2C using a hardware register * ixl_write_i2c_byte_reg - Writes 8 bit word over I2C using a hardware register
**/ **/
s32 s32
ixl_write_i2c_byte_reg(struct ixl_pf *pf, u8 byte_offset, ixl_write_i2c_byte_reg(struct ixl_pf *pf, u8 byte_offset,
u8 dev_addr, u8 data) u8 dev_addr, u8 data)
{ {
struct i40e_hw *hw = &pf->hw; struct i40e_hw *hw = &pf->hw;
s32 status = I40E_SUCCESS; s32 status = I40E_SUCCESS;
u32 reg = 0; u32 reg = 0;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesixl_wait_for_i2c_completion(struct i40e_hw *hw, u8 portnum)
if (timeout == 0) if (timeout == 0)
return I40E_ERR_TIMEOUT; return I40E_ERR_TIMEOUT;
else else
return status; return status;
} }
/** /**
* ixl_read_i2c_byte - Reads 8 bit word over I2C using a hardware register * ixl_read_i2c_byte_aq - Reads 8 bit word over I2C using an AQ command
**/ **/
s32 s32
ixl_read_i2c_byte_aq(struct ixl_pf *pf, u8 byte_offset, ixl_read_i2c_byte_aq(struct ixl_pf *pf, u8 byte_offset,
u8 dev_addr, u8 *data) u8 dev_addr, u8 *data)
{ {
struct i40e_hw *hw = &pf->hw; struct i40e_hw *hw = &pf->hw;
s32 status = I40E_SUCCESS; s32 status = I40E_SUCCESS;
u32 reg; u32 reg;
status = i40e_aq_get_phy_register(hw, status = i40e_aq_get_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
dev_addr, dev_addr, false,
byte_offset, byte_offset,
&reg, NULL); &reg, NULL);
if (status) if (status)
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read status %s, error %s\n", ixl_dbg(pf, IXL_DBG_I2C, "I2C byte read status %s, error %s\n",
i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status)); i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
else else
*data = (u8)reg; *data = (u8)reg;
return status; return status;
} }
/** /**
* ixl_write_i2c_byte - Writes 8 bit word over I2C using a hardware register * ixl_write_i2c_byte_aq - Writes 8 bit word over I2C using an AQ command
**/ **/
s32 s32
ixl_write_i2c_byte_aq(struct ixl_pf *pf, u8 byte_offset, ixl_write_i2c_byte_aq(struct ixl_pf *pf, u8 byte_offset,
u8 dev_addr, u8 data) u8 dev_addr, u8 data)
{ {
struct i40e_hw *hw = &pf->hw; struct i40e_hw *hw = &pf->hw;
s32 status = I40E_SUCCESS; s32 status = I40E_SUCCESS;
status = i40e_aq_set_phy_register(hw, status = i40e_aq_set_phy_register(hw,
I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE, I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
dev_addr, dev_addr, false,
byte_offset, byte_offset,
data, NULL); data, NULL);
if (status) if (status)
ixl_dbg(pf, IXL_DBG_I2C, "I2C byte write status %s, error %s\n", ixl_dbg(pf, IXL_DBG_I2C, "I2C byte write status %s, error %s\n",
i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status)); i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
return status; return status;
} }