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sys/dev/ixl/i40e_adminq.c
Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines | |||||
* i40e_free_adminq_asq - Free Admin Queue send rings | * i40e_free_adminq_asq - Free Admin Queue send rings | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
* This assumes the posted send buffers have already been cleaned | * This assumes the posted send buffers have already been cleaned | ||||
* and de-allocated | * and de-allocated | ||||
**/ | **/ | ||||
void i40e_free_adminq_asq(struct i40e_hw *hw) | void i40e_free_adminq_asq(struct i40e_hw *hw) | ||||
{ | { | ||||
i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); | |||||
i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); | i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); | ||||
} | } | ||||
/** | /** | ||||
* i40e_free_adminq_arq - Free Admin Queue receive rings | * i40e_free_adminq_arq - Free Admin Queue receive rings | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
* This assumes the posted receive buffers have already been cleaned | * This assumes the posted receive buffers have already been cleaned | ||||
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines | enum i40e_status_code i40e_init_asq(struct i40e_hw *hw) | ||||
/* allocate buffers in the rings */ | /* allocate buffers in the rings */ | ||||
ret_code = i40e_alloc_asq_bufs(hw); | ret_code = i40e_alloc_asq_bufs(hw); | ||||
if (ret_code != I40E_SUCCESS) | if (ret_code != I40E_SUCCESS) | ||||
goto init_adminq_free_rings; | goto init_adminq_free_rings; | ||||
/* initialize base registers */ | /* initialize base registers */ | ||||
ret_code = i40e_config_asq_regs(hw); | ret_code = i40e_config_asq_regs(hw); | ||||
if (ret_code != I40E_SUCCESS) | if (ret_code != I40E_SUCCESS) | ||||
goto init_adminq_free_rings; | goto init_config_regs; | ||||
/* success! */ | /* success! */ | ||||
hw->aq.asq.count = hw->aq.num_asq_entries; | hw->aq.asq.count = hw->aq.num_asq_entries; | ||||
goto init_adminq_exit; | goto init_adminq_exit; | ||||
init_adminq_free_rings: | init_adminq_free_rings: | ||||
i40e_free_adminq_asq(hw); | i40e_free_adminq_asq(hw); | ||||
return ret_code; | |||||
init_config_regs: | |||||
i40e_free_asq_bufs(hw); | |||||
init_adminq_exit: | init_adminq_exit: | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_init_arq - initialize ARQ | * i40e_init_arq - initialize ARQ | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines | static void i40e_resume_aq(struct i40e_hw *hw) | ||||
hw->aq.arq.next_to_use = 0; | hw->aq.arq.next_to_use = 0; | ||||
hw->aq.arq.next_to_clean = 0; | hw->aq.arq.next_to_clean = 0; | ||||
i40e_config_arq_regs(hw); | i40e_config_arq_regs(hw); | ||||
} | } | ||||
/** | /** | ||||
* i40e_set_hw_flags - set HW flags | |||||
* @hw: pointer to the hardware structure | |||||
**/ | |||||
static void i40e_set_hw_flags(struct i40e_hw *hw) | |||||
{ | |||||
struct i40e_adminq_info *aq = &hw->aq; | |||||
hw->flags = 0; | |||||
switch (hw->mac.type) { | |||||
case I40E_MAC_XL710: | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710)) { | |||||
hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; | |||||
hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; | |||||
/* The ability to RX (not drop) 802.1ad frames */ | |||||
hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; | |||||
} | |||||
break; | |||||
case I40E_MAC_X722: | |||||
hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | | |||||
I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722)) | |||||
hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_X722)) | |||||
hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= I40E_MINOR_VER_FW_REQUEST_FEC_X722)) | |||||
hw->flags |= I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE; | |||||
/* fall through */ | |||||
default: | |||||
break; | |||||
} | |||||
/* Newer versions of firmware require lock when reading the NVM */ | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= 5)) | |||||
hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= 8)) { | |||||
hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT; | |||||
hw->flags |= I40E_HW_FLAG_DROP_MODE; | |||||
} | |||||
if (aq->api_maj_ver > 1 || | |||||
(aq->api_maj_ver == 1 && | |||||
aq->api_min_ver >= 9)) | |||||
hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED; | |||||
} | |||||
/** | |||||
* i40e_init_adminq - main initialization routine for Admin Queue | * i40e_init_adminq - main initialization routine for Admin Queue | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
* | * | ||||
* Prior to calling this function, drivers *MUST* set the following fields | * Prior to calling this function, drivers *MUST* set the following fields | ||||
* in the hw->aq structure: | * in the hw->aq structure: | ||||
* - hw->aq.num_asq_entries | * - hw->aq.num_asq_entries | ||||
* - hw->aq.num_arq_entries | * - hw->aq.num_arq_entries | ||||
* - hw->aq.arq_buf_size | * - hw->aq.arq_buf_size | ||||
* - hw->aq.asq_buf_size | * - hw->aq.asq_buf_size | ||||
**/ | **/ | ||||
enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw) | enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw) | ||||
{ | { | ||||
struct i40e_adminq_info *aq = &hw->aq; | |||||
enum i40e_status_code ret_code; | |||||
u16 cfg_ptr, oem_hi, oem_lo; | u16 cfg_ptr, oem_hi, oem_lo; | ||||
u16 eetrack_lo, eetrack_hi; | u16 eetrack_lo, eetrack_hi; | ||||
enum i40e_status_code ret_code; | |||||
int retry = 0; | int retry = 0; | ||||
/* verify input for valid configuration */ | /* verify input for valid configuration */ | ||||
if ((hw->aq.num_arq_entries == 0) || | if (aq->num_arq_entries == 0 || | ||||
(hw->aq.num_asq_entries == 0) || | aq->num_asq_entries == 0 || | ||||
(hw->aq.arq_buf_size == 0) || | aq->arq_buf_size == 0 || | ||||
(hw->aq.asq_buf_size == 0)) { | aq->asq_buf_size == 0) { | ||||
ret_code = I40E_ERR_CONFIG; | ret_code = I40E_ERR_CONFIG; | ||||
goto init_adminq_exit; | goto init_adminq_exit; | ||||
} | } | ||||
i40e_init_spinlock(&hw->aq.asq_spinlock); | i40e_init_spinlock(&aq->asq_spinlock); | ||||
i40e_init_spinlock(&hw->aq.arq_spinlock); | i40e_init_spinlock(&aq->arq_spinlock); | ||||
/* Set up register offsets */ | /* Set up register offsets */ | ||||
i40e_adminq_init_regs(hw); | i40e_adminq_init_regs(hw); | ||||
/* setup ASQ command write back timeout */ | /* setup ASQ command write back timeout */ | ||||
hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; | hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; | ||||
/* allocate the ASQ */ | /* allocate the ASQ */ | ||||
Show All 10 Lines | enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw) | ||||
if (i40e_is_vf(hw)) | if (i40e_is_vf(hw)) | ||||
goto init_adminq_exit; | goto init_adminq_exit; | ||||
/* There are some cases where the firmware may not be quite ready | /* There are some cases where the firmware may not be quite ready | ||||
* for AdminQ operations, so we retry the AdminQ setup a few times | * for AdminQ operations, so we retry the AdminQ setup a few times | ||||
* if we see timeouts in this first AQ call. | * if we see timeouts in this first AQ call. | ||||
*/ | */ | ||||
do { | do { | ||||
ret_code = i40e_aq_get_firmware_version(hw, | ret_code = i40e_aq_get_firmware_version(hw, | ||||
&hw->aq.fw_maj_ver, | &aq->fw_maj_ver, | ||||
&hw->aq.fw_min_ver, | &aq->fw_min_ver, | ||||
&hw->aq.fw_build, | &aq->fw_build, | ||||
&hw->aq.api_maj_ver, | &aq->api_maj_ver, | ||||
&hw->aq.api_min_ver, | &aq->api_min_ver, | ||||
NULL); | NULL); | ||||
if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) | if (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT) | ||||
break; | break; | ||||
retry++; | retry++; | ||||
i40e_msec_delay(100); | i40e_msec_delay(100); | ||||
i40e_resume_aq(hw); | i40e_resume_aq(hw); | ||||
} while (retry < 10); | } while (retry < 10); | ||||
if (ret_code != I40E_SUCCESS) | if (ret_code != I40E_SUCCESS) | ||||
goto init_adminq_free_arq; | goto init_adminq_free_arq; | ||||
/* | |||||
* Some features were introduced in different FW API version | |||||
* for different MAC type. | |||||
*/ | |||||
i40e_set_hw_flags(hw); | |||||
/* get the NVM version info */ | /* get the NVM version info */ | ||||
i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, | i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, | ||||
&hw->nvm.version); | &hw->nvm.version); | ||||
i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); | i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); | ||||
i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); | i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); | ||||
hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; | hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; | ||||
i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); | i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); | ||||
i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), | i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), | ||||
&oem_hi); | &oem_hi); | ||||
i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), | i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), | ||||
&oem_lo); | &oem_lo); | ||||
hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; | hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; | ||||
/* The ability to RX (not drop) 802.1ad frames was added in API 1.7 */ | if (aq->api_maj_ver > I40E_FW_API_VERSION_MAJOR) { | ||||
if ((hw->aq.api_maj_ver > 1) || | |||||
((hw->aq.api_maj_ver == 1) && | |||||
(hw->aq.api_min_ver >= 7))) | |||||
hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; | |||||
if (hw->mac.type == I40E_MAC_XL710 && | |||||
hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && | |||||
hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { | |||||
hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; | |||||
} | |||||
/* Newer versions of firmware require lock when reading the NVM */ | |||||
if ((hw->aq.api_maj_ver > 1) || | |||||
((hw->aq.api_maj_ver == 1) && | |||||
(hw->aq.api_min_ver >= 5))) | |||||
hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; | |||||
if (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) { | |||||
ret_code = I40E_ERR_FIRMWARE_API_VERSION; | ret_code = I40E_ERR_FIRMWARE_API_VERSION; | ||||
goto init_adminq_free_arq; | goto init_adminq_free_arq; | ||||
} | } | ||||
/* pre-emptive resource lock release */ | /* pre-emptive resource lock release */ | ||||
i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); | i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); | ||||
hw->nvm_release_on_done = FALSE; | hw->nvm_release_on_done = FALSE; | ||||
hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; | ||||
ret_code = I40E_SUCCESS; | ret_code = I40E_SUCCESS; | ||||
/* success! */ | /* success! */ | ||||
goto init_adminq_exit; | goto init_adminq_exit; | ||||
init_adminq_free_arq: | init_adminq_free_arq: | ||||
i40e_shutdown_arq(hw); | i40e_shutdown_arq(hw); | ||||
init_adminq_free_asq: | init_adminq_free_asq: | ||||
i40e_shutdown_asq(hw); | i40e_shutdown_asq(hw); | ||||
init_adminq_destroy_spinlocks: | init_adminq_destroy_spinlocks: | ||||
i40e_destroy_spinlock(&hw->aq.asq_spinlock); | i40e_destroy_spinlock(&aq->asq_spinlock); | ||||
i40e_destroy_spinlock(&hw->aq.arq_spinlock); | i40e_destroy_spinlock(&aq->arq_spinlock); | ||||
init_adminq_exit: | init_adminq_exit: | ||||
return ret_code; | return ret_code; | ||||
} | } | ||||
/** | /** | ||||
* i40e_shutdown_adminq - shutdown routine for the Admin Queue | * i40e_shutdown_adminq - shutdown routine for the Admin Queue | ||||
* @hw: pointer to the hardware structure | * @hw: pointer to the hardware structure | ||||
Show All 28 Lines | u16 i40e_clean_asq(struct i40e_hw *hw) | ||||
struct i40e_asq_cmd_details *details; | struct i40e_asq_cmd_details *details; | ||||
u16 ntc = asq->next_to_clean; | u16 ntc = asq->next_to_clean; | ||||
struct i40e_aq_desc desc_cb; | struct i40e_aq_desc desc_cb; | ||||
struct i40e_aq_desc *desc; | struct i40e_aq_desc *desc; | ||||
desc = I40E_ADMINQ_DESC(*asq, ntc); | desc = I40E_ADMINQ_DESC(*asq, ntc); | ||||
details = I40E_ADMINQ_DETAILS(*asq, ntc); | details = I40E_ADMINQ_DETAILS(*asq, ntc); | ||||
while (rd32(hw, hw->aq.asq.head) != ntc) { | while (rd32(hw, hw->aq.asq.head) != ntc) { | ||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, | ||||
"ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); | "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); | ||||
if (details->callback) { | if (details->callback) { | ||||
I40E_ADMINQ_CALLBACK cb_func = | I40E_ADMINQ_CALLBACK cb_func = | ||||
(I40E_ADMINQ_CALLBACK)details->callback; | (I40E_ADMINQ_CALLBACK)details->callback; | ||||
i40e_memcpy(&desc_cb, desc, sizeof(struct i40e_aq_desc), | i40e_memcpy(&desc_cb, desc, sizeof(struct i40e_aq_desc), | ||||
I40E_DMA_TO_DMA); | I40E_DMA_TO_DMA); | ||||
cb_func(hw, &desc_cb); | cb_func(hw, &desc_cb); | ||||
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines | if (hw->aq.asq.count == 0) { | ||||
status = I40E_ERR_QUEUE_EMPTY; | status = I40E_ERR_QUEUE_EMPTY; | ||||
goto asq_send_command_error; | goto asq_send_command_error; | ||||
} | } | ||||
val = rd32(hw, hw->aq.asq.head); | val = rd32(hw, hw->aq.asq.head); | ||||
if (val >= hw->aq.num_asq_entries) { | if (val >= hw->aq.num_asq_entries) { | ||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | ||||
"AQTX: head overrun at %d\n", val); | "AQTX: head overrun at %d\n", val); | ||||
status = I40E_ERR_QUEUE_EMPTY; | status = I40E_ERR_ADMIN_QUEUE_FULL; | ||||
goto asq_send_command_error; | goto asq_send_command_error; | ||||
} | } | ||||
details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); | details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); | ||||
if (cmd_details) { | if (cmd_details) { | ||||
i40e_memcpy(details, | i40e_memcpy(details, | ||||
cmd_details, | cmd_details, | ||||
sizeof(struct i40e_asq_cmd_details), | sizeof(struct i40e_asq_cmd_details), | ||||
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines | if (buff != NULL) { | ||||
*/ | */ | ||||
desc_on_ring->params.external.addr_high = | desc_on_ring->params.external.addr_high = | ||||
CPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa)); | CPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa)); | ||||
desc_on_ring->params.external.addr_low = | desc_on_ring->params.external.addr_low = | ||||
CPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa)); | CPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa)); | ||||
} | } | ||||
/* bump the tail */ | /* bump the tail */ | ||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n"); | i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n"); | ||||
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, | ||||
buff, buff_size); | buff, buff_size); | ||||
(hw->aq.asq.next_to_use)++; | (hw->aq.asq.next_to_use)++; | ||||
if (hw->aq.asq.next_to_use == hw->aq.asq.count) | if (hw->aq.asq.next_to_use == hw->aq.asq.count) | ||||
hw->aq.asq.next_to_use = 0; | hw->aq.asq.next_to_use = 0; | ||||
if (!details->postpone) | if (!details->postpone) | ||||
wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); | wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); | ||||
Show All 29 Lines | if (retval != 0) { | ||||
retval); | retval); | ||||
/* strip off FW internal code */ | /* strip off FW internal code */ | ||||
retval &= 0xff; | retval &= 0xff; | ||||
} | } | ||||
cmd_completed = TRUE; | cmd_completed = TRUE; | ||||
if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) | if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK) | ||||
status = I40E_SUCCESS; | status = I40E_SUCCESS; | ||||
else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY) | |||||
status = I40E_ERR_NOT_READY; | |||||
else | else | ||||
status = I40E_ERR_ADMIN_QUEUE_ERROR; | status = I40E_ERR_ADMIN_QUEUE_ERROR; | ||||
hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; | hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; | ||||
} | } | ||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, | i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, | ||||
"AQTX: desc and buffer writeback:\n"); | "AQTX: desc and buffer writeback:\n"); | ||||
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); | ||||
/* save writeback aq if requested */ | /* save writeback aq if requested */ | ||||
if (details->wb_desc) | if (details->wb_desc) | ||||
i40e_memcpy(details->wb_desc, desc_on_ring, | i40e_memcpy(details->wb_desc, desc_on_ring, | ||||
sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA); | sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA); | ||||
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines | i40e_memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc), | ||||
I40E_DMA_TO_NONDMA); | I40E_DMA_TO_NONDMA); | ||||
datalen = LE16_TO_CPU(desc->datalen); | datalen = LE16_TO_CPU(desc->datalen); | ||||
e->msg_len = min(datalen, e->buf_len); | e->msg_len = min(datalen, e->buf_len); | ||||
if (e->msg_buf != NULL && (e->msg_len != 0)) | if (e->msg_buf != NULL && (e->msg_len != 0)) | ||||
i40e_memcpy(e->msg_buf, | i40e_memcpy(e->msg_buf, | ||||
hw->aq.arq.r.arq_bi[desc_idx].va, | hw->aq.arq.r.arq_bi[desc_idx].va, | ||||
e->msg_len, I40E_DMA_TO_NONDMA); | e->msg_len, I40E_DMA_TO_NONDMA); | ||||
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n"); | i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n"); | ||||
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, | i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, | ||||
hw->aq.arq_buf_size); | hw->aq.arq_buf_size); | ||||
/* Restore the original datalen and buffer address in the desc, | /* Restore the original datalen and buffer address in the desc, | ||||
* FW updates datalen to indicate the event message | * FW updates datalen to indicate the event message | ||||
* size | * size | ||||
*/ | */ | ||||
bi = &hw->aq.arq.r.arq_bi[ntc]; | bi = &hw->aq.arq.r.arq_bi[ntc]; | ||||
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